ADN2814ACPZ-500RL7 Datasheet ADN2814ACPZ, ADN2814ACPZ-500RL7, ADN2814ACPZ-RL7 | P16-P18

Data Sheet ADN2814

Rev. C | Page 15 of 28

At medium jitter frequencies, the gain and tuning range of the

VCO are not large enough to track input jitter. In this case, the

VCO control voltage becomes large and saturates, and the VCO

frequency dwells at one extreme of its tuning range or at the

other. The size of the VCO tuning range, therefore, has only a

small effect on the jitter accommodation. The delay-locked loop

control voltage is now larger, and therefore the phase shifter

takes on the burden of tracking the input jitter. The phase

shifter range, in UI, can be seen as a broad plateau on the jitter

tolerance curve. The phase shifter has a minimum range of

2 UI at all data rates.

The gain of the loop integrator is small for high jitter

frequencies; therefore, larger phase differences are needed to

make the loop control voltage large enough to tune the range of

the phase shifter. Large phase errors at high jitter frequencies

cannot be tolerated. In this region, the gain of the integrator

determines the jitter accommodation. Because the gain of the

loop integrator declines linearly with frequency, jitter accom-

modation is lower with higher jitter frequency. At the highest

frequencies, the loop gain is very small, and little tuning of the

phase shifter can be expected. In this case, jitter accommodation is

determined by the eye opening of the input data, the static

phase error, and the residual loop jitter generation. The jitter

accommodation is roughly 0.5 UI in this region. The corner

frequency between the declining slope and the flat region is

the closed loop bandwidth of the delay-locked loop, which is

roughly 1.0 MHz at 622 Mb/s.

ADN2814 Data Sheet

Rev. C | Page 16 of 28

FUNCTIONAL DESCRIPTION

FREQUENCY ACQUISITION

The ADN2814 acquires frequency from the data over a range of

data frequencies from 10 Mb/s to 675 Mb/s. The lock detector

circuit compares the frequency of the VCO and the frequency

of the incoming data. When these frequencies differ by more

than 1000 ppm, LOL is asserted. This initiates a frequency

acquisition cycle. The VCO frequency is reset to the bottom of

its range, which is 10 MHz. The frequency detector then

compares this VCO frequency and the incoming data frequency

and increments the VCO frequency, if necessary. Initially, the

VCO frequency is incremented in large steps to aid fast acquisi-

tion. As the VCO frequency approaches the data frequency, the

step size is reduced until the VCO frequency is within 250 ppm

of the data frequency, at which point LOL is deasserted.

Once LOL is deasserted, the frequency-locked loop is turned

off. The PLL/DLL pulls in the VCO frequency the rest of the

way until the VCO frequency equals the data frequency.

The frequency loop requires a single external capacitor between

CF1 and CF2, Pin 14 and Pin 15. A 0.47 μF ± 20%, X7R ceramic

chip capacitor with < 10 nA leakage current is recommended.

Leakage current of the capacitor can be calculated by dividing

the maximum voltage across the 0.47 μF capacitor, ~3 V, by the

insulation resistance of the capacitor. The insulation resistance

of the 0.47 μF capacitor should be greater than 300 MΩ.

LIMITING AMPLIFIER

The limiting amplifier has differential inputs (PIN/NIN), which

are internally terminated with 50 Ω to an on-chip voltage

reference (VREF = 2.5 V typically). The inputs are typically

ac-coupled externally, although dc coupling is possible as long

as the input common-mode voltage remains above 2.5 V (see

Figure 27 to Figure 29 in the Applications Information section).

Input offset is factory trimmed to achieve better than 3.3 mV

typical sensitivity with minimal drift. The limiting amplifier can

be driven differentially or single-ended.

SLICE ADJUST

The quantizer slicing level can be offset by ±100 mV to mitigate

the effect of amplified spontaneous emission (ASE) noise or

duty cycle distortion by applying a differential voltage input of

up to ±0.95 V to SLICEP/SLICEN inputs. If no adjustment of

the slice level is needed, SLICEP/SLICEN should be tied to

VEE. The gain of the slice adjustment is ~0.11 V/V.

LOSS-OF-SIGNAL (LOS) DETECTOR

The receiver front-end LOS detector circuit detects when the

input signal level has fallen below a user-adjustable threshold.

The threshold is set with a single external resistor from Pin 9,

THRADJ, to VEE. The LOS comparator trip point vs. the

resistor value is illustrated in Figure 6. If the input level to the

ADN2814 drops below the programmed LOS threshold, the

output of the LOS detector, LOS Pin 22, is asserted to a Logic 1.

The LOS detector’s response time is ~500 ns by design, but is

dominated by the RC time constant in ac-coupled applications.

The LOS pin defaults to active high. However, by setting Bit

CTRLC[2] to 1, the LOS pin is configured as active low.

There is typically 6 dB of electrical hysteresis designed into the

LOS detector to prevent chatter on the LOS pin. If the input

level drops below the programmed LOS threshold causing the

LOS pin to assert, the LOS pin is not deasserted until the input

level has increased to 6 dB (2×) above the LOS threshold (see

Figure 19).

HYSTERESIS

LOS OUTPUT

INPUT LEVEL

LOS THRESHOLD

INPUT VOLTAGE (V

DIFF

)

04949-019

Figure 19. LOS Detector Hysteresis

The LOS detector and the SLICE level adjust can be used

simultaneously on the ADN2814. This means that any offset

added to the input signal by the SLICE adjust pins does not

affect the LOS detector’s measurement of the absolute input

level.

Data Sheet ADN2814

Rev. C | Page 17 of 28

LOCK DETECTOR OPERATION

The lock detector on the ADN2814 has three modes of

operation: normal mode, REFCLK mode, and static LOL mode.

Normal Mode

In normal mode, the ADN2814 is a continuous rate CDR that

locks onto any data rate from 10 Mb/s to 675 Mb/s without the

use of a reference clock as an acquisition aid. In this mode, the

lock detector monitors the frequency difference between the

VCO and the input data frequency and deasserts the loss of lock

signal, which appears on Pin 16, LOL, when the VCO is within

250 ppm of the data frequency. This enables the D/PLL, which

pulls the VCO frequency in the remaining amount and acquires

phase lock. Once locked, if the input frequency error exceeds

1000 ppm (0.1%), the loss-of-lock signal is reasserted and

control returns to the frequency loop, which begins a new

frequency acquisition starting at the lowest point in the VCO

operating range, 10 MHz. The LOL pin remains asserted until

the VCO locks onto a valid input data stream to within

250 ppm frequency error. This hysteresis is shown in Figure 20.

LOL

0–250 250 1000 f

VCO

ERROR

(ppm)

–1000

04949-020

Figure 20. Transfer Function of LOL

LOL Detector Operation Using a Reference Clock

In REFCLK mode, a reference clock is used as an acquisition aid

to lock the ADN2814 VCO. Lock-to-reference mode is enabled

by setting CTRLA[0] to 1. The user also needs to write to the

CTRLA[7:6] and CTRLA[5:2] bits to set the reference

frequency range and the divide ratio of the data rate with

respect to the reference frequency. For more details, see the

Reference Clock (Optional) section. In this mode, the lock

detector monitors the difference in frequency between the

divided down VCO and the divided down reference clock. The

loss-of-lock signal, which appears on Pin 16, LOL, is deasserted

when the VCO is within 250 ppm of the desired frequency. This

enables the D/PLL, which pulls the VCO frequency in the

remaining amount with respect to the input data and acquires

phase lock. Once locked, if the input frequency error exceeds

1000 ppm (0.1%), the loss-of-lock signal is reasserted and

control returns to the frequency loop, which reacquires with

respect to the reference clock. The LOL pin remains asserted

until the VCO frequency is within 250 ppm of the desired

frequency. This hysteresis is shown in Figure 20.

Static LOL Mode

The ADN2814 implements a static LOL feature, which indicates

if a loss-of-lock condition has ever occurred and remains

asserted, even if the ADN2814 regains lock, until the static LOL

bit is manually reset. The I

C register bit, MISC[4], is the static

LOL bit. If there is ever an occurrence of a loss-of-lock condition,

this bit is internally asserted to logic high. The MISC[4] bit

remains high even after the ADN2814 has reacquired lock to a

new data rate. This bit can be reset by writing a 1 followed by 0

to I

C Register Bit CTRLB[6]. Once reset, the MISC[4] bit

remains deasserted until another loss-of-lock condition occurs.

Writing a 1 to I

C Register Bit CTRLB[7] causes the LOL pin,

Pin 16, to become a static LOL indicator. In this mode, the LOL

pin mirrors the contents of the MISC[4] bit and has the

functionality described in the previous paragraph. The CTRLB[7]

bit defaults to 0. In this mode, the LOL pin operates in the

normal operating mode, that is, it is asserted only when the

ADN2814 is in acquisition mode and deasserts when the

ADN2814 has reacquired lock.

HARMONIC DETECTOR

The ADN2814 provides a harmonic detector, which detects

whether or not the input data has changed to a lower harmonic

of the data rate that the VCO is currently locked onto. For

example, if the input data instantaneously changes from OC-12,

622.08 Mb/s to an OC-3, 155.52 Mb/s bit stream, this could be

perceived as a valid OC-12 bit stream, because the OC-3 data

pattern is exactly 4× slower than the OC-12 pattern. Therefore,

if the change in data rate is instantaneous, a 101 pattern at OC-3

would be perceived by the ADN2814 as a 111100001111 pattern

at OC-12. If the change to a lower harmonic is instantaneous, a

typical CDR could remain locked at the higher data rate.

The ADN2814 implements a harmonic detector that automati-

cally identifies whether or not the input data has switched to a

lower harmonic of the data rate that the VCO is currently

locked onto. When a harmonic is identified, the LOL pin is

asserted and a new frequency acquisition is initiated. The

ADN2814 automatically locks onto the new data rate, and the

LOL pin is deasserted.

However, the harmonic detector does not detect higher

harmonics of the data rate. If the input data rate switches to a

higher harmonic of the data rate, then the VCO is currently

locked onto, the VCO loses lock, the LOL pin is asserted, and a

new frequency acquisition is initiated. The ADN2814

automatically locks onto the new data rate.

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ADN2814ACPZ-500RL7

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Manufacturer:

Analog Devices Inc.

Description:

Timers & Support Products 12 Mbps - 1.3G ADN2812 Derivative IC.

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ADN2814ACPZ-500RL7

ADN2814ACPZ-500RL7

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