MAX3816A
I
2
C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
6 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 DRVR_EN
Driver Enable Input, LVTTL/LVCMOS. Set high to enable all data and clock drivers for normal
operation. Set low to disable drivers, permitting isolation of cable bus from display bus.
2 V
CC
Power Supply for Cable Side. In the DDC application, connect to DDC +5V. Connect 10μF or larger
bypass capacitor as shown in Figure 6.
3 CLOCK_C I
2
C Cable-Side Clock with Cable Driver, CMOS Input/Output. Connect a 47k pullup resistor to V
CC
.
4 GND_REF
Cable-Side Ground Return. Connect directly to cable DDC ground wire. The MAX3816A circuitry uses
the video source DDC GND as a threshold reference. Also connect 10μF or larger bypass capacitors
as shown in Figure 6.
5 DATA_C I
2
C Cable-Side Data with Cable Driver, CMOS Input/Output. Connect a 47k pullup resistor to V
CC
.
6 GND_REF Cable-Side Ground Return (Alternate). Connected internally to pin 4 above.
7 V
CC
Power Supply for Cable Side (Alternate). Connected internally to pin 2 above.
8, 9, 10 DNC Do Not Connect
11 V
DD
Power Supply for Display Side and Core Circuitry. Connect bypass capacitor as shown in Figure 6.
12 DATA_D
I
2
C Display-Side Data, CMOS Input/Output. Connect a 2.2k pullup resistor to V
DD
for V
DD
= 3.3V,
or a 3.3k pullup resistor to V
DD
for V
DD
= 5V.
13 V
SS
Ground for Display Side and Core Circuitry. Connect bypass capacitors as shown in Figure 6.
14 CLOCK_D
I
2
C Display-Side Clock, CMOS Input/Output. Connect a 2.2k pullup resistor to V
DD
for V
DD
= 3.3V,
or a 3.3k pullup resistor to V
DD
for V
DD
= 5V.
15 V
SS_T
Must Be Connected to V
SS
for Normal Operation
16 MODE
Mode Setting Input, LVTTL/LVCMOS. Force high for parallel mode (normal operation) and force low for
serial operation.
Theory of Operation
The MAX3816A has parallel and series modes. The
parallel mode is preferred for applications where high
tolerance to noncompliant source and sink devices is
desired (noncompliant V
OL
from displays and noncom-
pliant V
IH
from sources are common). Further, the par-
allel mode can be operated with other speed-up
devices on the same bus, either active (DRVR_EN = HI)
or in bypass (DRVR_EN = LO).
Series mode is preferred for applications where high
tolerance to ground offset or noise between and source
and sink is needed. Series mode also isolates display
circuits from transmission line reflections in very long
cables, providing full isolation between cable and dis-
play buses. For in-display applications, series mode
can provide level shifting between the 5V cable DDC
and 3.3V display internal DDC.
A single MAX3816A is applied at the display side of the
video link to compensate for excessive cable capaci-
tance. The overall operation of the MAX3816A, for
either the DATA or CLOCK signal, can be summarized
as follows (Figures 1a and 1b).
1) High state. Drivers off. Level sensing on.
If no client device is controlling the “wired-AND” bus
from either the source or display side, all device dri-
vers are off and the bus (including the MAX3816A)
is waiting in the high state. The pullup resistors on
each side are holding the bus up to V
CC
on the
source side and V
DD
on the display side.
2) High-to-low transition. Drivers assert low. Level
sensing off (Holdoff).
A change of state is initiated by any device driver
pulling low. Once the signal transitions below 75%
of the power supply, the MAX3816A drives both the
source and display sides toward ground with a low-
impedance driver, level sensing is turned off, and
the holdoff timer is started. The source side is
pulled down to the level of the V
SS
. This is accom-
plished using a low-impedance n-channel buffer
that is designed to drive a 1 meter (60pF) to 60
