MAX3816A
I
2
C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
_______________________________________________________________________________________ 7
meter (> 3000pF) cable with a controlled slew-rate.
Similarly, the display side is pulled down to V
SS
with
a controlled slew rate, open-drain n-channel MOS
device. These buffers stay on for 1.75µs.
3) Low state. Level sensing off (Holdoff).
Level sensing remains off until the completion of the
holdoff period, which is 2.5µs on both the clock and
data channels.
In series mode, drivers maintain low level (at or
below V
HOLD
). Either the client pulldowns sustain
the level below V
OL
, or the MAX3816A sustains the
level at V
HOLD
if no other driver on the same node
is pulling down. This action is in support of the
“wired-AND” function across source and display
sides.
4) Low state, drivers off. Level sensing on.
After the MAX3816A holdoff time completes, level
sensing resumes.
In series mode, the MAX3816A supports a “wired-
AND” connection between source and display
sides; returning to the high state is supported only
when all client sources turn off. If either the source
or display side releases the bus, but not both, a
MAX3816A level-sensing buffer senses the transi-
tion at V
TRIGIL
, supporting the existing low state by
clamping the voltage to V
HOLD
and waiting for the
remaining side to release the bus.
5) Low-to-high transition. Drivers on. Level sensing
off (Holdoff).
A change of state is initiated when no device is
holding the bus low on both source and display
sides. When both sides exceed their respective
V
TRIGIL
levels, the source side turns on a slew-rate
controlled open-drain p-channel device, pulling up
to V
CC
for 1.75µs. Simultaneously, the display side
is released and the pullup resistors pull the display-
side bus up to V
DD
, as per normal I
2
C operation.
6) High state. Drivers off. Level sensing off
(Holdoff).
During holdoff, no transitions are sensed. The high
state is maintained by external pullup resistors. Upon
the end of holdoff, when the cable and display levels
are above 85%, the state machine transitions to state
(1); otherwise, it waits until levels raise above 85% to
transition to state (1). Data, but not clock, has anoth-
er exit from state (6) to (1) upon data source or data
display levels dropping below 60%.
I
2
C continuous clock applications are not recommend-
ed for the MAX3816A. The MAX3816A is optimized for
DDC applications with a noncontinuous clock.
Detailed Description
The MAX3816A DDC/I
2
C 2-wire extender consists of
two controllers with level-shifters, cable drivers, display
drivers, and level-sensing circuitry (Figure 2).
Controllers and Level Shifters
The MAX3816A functionality is governed by two con-
trollers, one for CLOCK and one for DATA. Bidirectional
signaling is fully supported on both CLOCK and DATA.
The primary function of the controllers is to receive the
state-change information from the source- and display-
side level-sense circuitry and support the “wired-AND”
function between the two. When the state changes, a
holdoff period is timed during which the source and
display drivers assert the next state, high or low, and all
input sensing is ignored while I/O transients settle
(Figure 3). The holdoff period is approximately 2.5µs.
The cable transmission-line termination feature is active
only during the first 1.75µs of holdoff, sufficiently long
enough to absorb roundtrip reflections from a 60m
cable.
In series mode, the CLOCK and DATA controllers iso-
late the source electronics from the display electronics.
The cable side of the MAX3816A is referenced to V
CC
and GND_REF, and the display side is referenced to
V
DD
and V
SS
. This power scheme provides tolerance to
offset and noise between the source and display
devices.
Cable Drivers
The low-impedance cable drivers (Figure 10) can
charge and discharge at least 3000pF of capacitive
cable load within the I
2
C rise and fall time limits. The
drivers each incorporate a slew-rate limiter to control
the amount of high-frequency energy transmitted. The
cable drivers also provide a back termination imped-
ance of approximately 60Ω to absorb transmission-line
reflections returning to the driver. The cable drivers
each include a high-state current-limiting feature to
clamp the output current to less than 16mA.
After 1.75µs of driver assertion, following a decision to
transition, the low-impedance drivers are turned off.
Subsequently, when another device asserts a new
state, it does not have to work against the low imped-
ance of the MAX3816A.
MAX3816A
I
2
C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
8 _______________________________________________________________________________________
LOW
STATE
HIGH
STATE
CLOCK_D > 17.5% AND CLOCK_C > 12.5%
CLOCK_C “OR” CLOCK_D < 75%
NOTES:
1) STATE CHANGE CONDITIONS ARE IN ITALICS. TRANSITION ACTIONS ARE UNDERLINED.
2) THE DATA CHANNEL STATE MACHINE IS IDENTICAL AND SYMMETRIC, EXCEPT THAT HOLDOFF TIME IS 2.0μs INSTEAD OF 2.5μs.
ALSO, IN ADDITION TO THE 85% CONDITION TO EXIT STATE 6, DATA HAS AN ADDITIONAL EXIT: DATA_C “OR” DATA_D < 60%.
3) DEPENDENT ON MODE PIN 16: MODE = LOW FOR SERIAL OPERATION (DRIVERS HOLD); MODE = HIGH FOR PARALLEL OPERATION (DRIVERS OFF).
HOLDOFF TIMER = START
HOLDOFF TIMER = START
5
SENSE OFF
DRIVERS ON
6
SENSE OFF
DRIVERS OFF
4
SENSE ON
(NOTE 3)
RAMP
UP
RAMP
DOWN
3
SENSE OFF
(NOTE 3)
1
SENSE ON
DRIVERS OFF
2
SENSE OFF
DRIVERS ON
HOLDOFF TIMER = 1.75
s
μ
HOLDOFF TIMER = 1.75
s
μ
HOLDOFF TIMER 2.5
s
“AND”
CLOCK_C “AND” CLOCK_D > 85%
μ
HOLDOFF TIMER = 2.5
s
μ
Figure 1a. Clock State Machine Diagram
Locally, connect a 47kΩ pullup resistor from CLOCK_C
and DATA_C to V
CC
. This assumes that a 1.65kΩ
pullup resistor resides at the opposite end of each
channel.
Display Drivers
The display drivers (Figure 11) are typical open-drain
pulldown devices capable of discharging up to 400pF
of capacitive load within the I
2
C fall-time limits.
Locally, connect a 2.2kΩ pullup resistor from CLOCK_D
and DATA_D to V
DD
for V
DD
= 3.3V, or a 3.3kΩ pullup
resistor to V
DD
for V
DD
= 5V.
Level Sense
The MAX3816A’s level-sensing circuitry monitors the
incoming data for state transitions. When the CLOCK or
DATA signal is high and drops below V
TRIGIH
, the con-
troller ramps the outputs low. When the DATA and
CLOCK are low and both rise above V
TRIGI
L
, refer-
enced to GND_REF on the source side or V
SS
on the
display side, the output drives the level high.
MAX3816A
I
2
C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
_______________________________________________________________________________________ 9
V
XX
DDC V
IH
= 70% V
XX
DDC V
IL
= 30% V
XX
DDC V
OL
(max) = 0.4V
GND
GND
V
XX
DDC V
IH
= 70% V
XX
DDC V
IL
= 30% V
XX
DDC V
OL
(max) = 0.4V
CABLE/
SOURCE
SIDE
(NOTE 1)
STATE
NUMBER
DISPLAY
SIDE
(NOTE 1)
V
TRIGIH
= 75% V
XX
0μsHOLDOFF TIMER
NOTES:
1) THIS EXAMPLE APPLIES TO TRANSMISSION IN EITHER DIRECTION. SOURCE TO DISPLAY IS SHOWN.
2) V
XX
IS USED GENERICALLY FOR THE VOLTAGE AT THE V
CC
OR V
DD
PINS.
V
TRIGIH
= 12.5% V
CC
CLOCK_C,
17.5% V
DD
CLOCK_D
V
HOLD
= 15% V
CC
CLOCK_C,
20% V
DD
CLOCK_D
0μs 1.75μs 2.5μs1.75μs 2.5μs
1 124
3
5
6
Figure 1b. Signal Waveform Example Showing States

MAX3816ACUE+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Video ICs TMDS Digi Video EQ for HDMI/DVI Cables
Lifecycle:
New from this manufacturer.
Delivery:
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