FL7740
www.onsemi.com
10
Primary Side Constant Voltage Regulation
FL7740 utilizes auxiliary winding to detect output
voltage during secondary side diode conduction time
(=T
DIS
). The true output voltage level without secondary
diode forward voltage drop is at the end of secondary
diode conduction time. In order to detect the right output
voltage, 85% of T
DIS
at previous switching cycle is
sampling time for V
EAV
detection at current switching
cycle.
S
/
H
VS
V
REF
Error
Amp.
V
EAV
COMV
T
DIS
detection
Duty
Control
N
AUX
V
IN.PK
Figure 15. Primary Side Regulation
VS
GATE
85% T
DIS
at previous
switching
T
DIS
V
EAV
sampling
Figure 16. V
EAV
Detection
The sampled V
EAV
is compared with 3.5 V V
REF
at the
input of the error amplifier. Several hundreds nF
capacitor is connected to the output of the error amplifier
at COMV pin to keep feedback loop slow in PFC control.
COMV voltage controls duty to regulate V
EAV
same as
V
REF
in the system.
Turn-on time is controlled by both COMV voltage and
V
IN.PK
information in line feedforward operation in order
to keep the constant COMV voltage in the wide input
voltage range. So, turn-on time is proportional to COMV
voltage and inversely proportional to V
IN.PK
.
Startup
After plug-in, external VDD capacitor is quickly
charged by internal HV biasing supply. Even after VDD
is higher than 16 V V
DD-ON
, internal HV biasing is still
enabled for 500 ms, so HV biasing can relieve VDD
capacitor discharging until auxiliary winding builds up
VDD voltage.
In order to speed up large output capacitor charging
without overshoot, FL7740 starts with proportional gain
during startup sequence (SS1 + SS2) by using internal
resistive load at the output of the error amplifier.
In SS1, CCM prevent operation is enabled for the initial
2 ms. When output voltage is 0 V, deep CCM could be
entered at initial startup and CS could touch OCP level
with startup failure. So, pulse-by-pulse current limit is
0.2 V and switching frequency is 22 kHz during the 2 ms
CCM prevent time. Also, duty is gradually increased for
26 ms for soft startup. Once 5 V pulled-up COMV
voltage drops less than 4.5 V as V
EAV
is close to V
REF
,
SS1 is ended. Maximum SS1 time is limited up to 100
ms.
In SS2, V
COMV
drops from 5 V and goes into p-gain
steady state in which V
EAV
is little bit lower than V
REF
due to the error amplifier input error in p-gain. Once p-
gain steady state is settled down in 45 ms, SS2 is
finished at min. V
COMV
range not to make overshoot
when transitioning to i-gain after SS2. FL7740 ends SS2
by monitoring V
IN
1.5 ms after V
IN.PK
detection moment
where V
COMV
is generally in the min. range.
V
COMV
Duty
V
EAV
V
IN
V
REF
Startup time by P-
gain I
-gain
45
ms
4.
5 V
26
ms soft start
2 ms CCM prevent
5.
0
V
V
IN.
PK
1
.5 ms
SS
1 SS2
Figure 17. Startup Sequence
Dynamic CV Regulation
Due to the narrow loop bandwidth, PFC controller
generally does not guarantee good CV regulation at load
transient. Especially in secondary side regulation,
primary side controller does not know the output voltage
level and it only monitors the output of feedback signal
through opto-coupler. Therefore, output voltage
undershoot is severely happened at no to full load
transient in the conventional SSR PFC control.
In order to overcome this, FL7740 utilizes the benefit of
PSR with ON semiconductor’s proprietary dynamic duty
control by monitoring the output voltage. For example,
when V
EAV
is less than V
UVD.EN
(Under Voltage Dynamic
Enable threshold), duty is quickly increased not to allow
undershoot anymore. Once V
EAV
rises higher than
V
UVD.DIS
(Under Voltage Dynamic Disable threshold),
duty quickly drops and follows COMV voltage. During
the V
EAV
hiccup operation, COMV voltage slowly
increases and dynamic operation is terminated when
COMV voltage is close to steady state level.
