FL7740MX Datasheet FL7740MX | P4-P6

FL7740

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4

MAXIMUM RATINGS (Note 1)

1. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device

functionality should not be assumed, damage may occur and reliability may be affected.

2. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe

Operating parameters.

3. This device series incorporates ESD protection and is tested by the following methods:

ESD Human Body Model tested per AEC-Q100-002 (EIA/JESD22-A114)

ESD Machine Model tested per AEC-Q100-003 (EIA/JESD22-A115)

Latchup Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78

RECOMMENDED OPERATING RANGES (Note 4)

4. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses

beyond the Recommended Operating Ranges limits may affect device reliability.

Rating

Symbol

Value

Unit

HV Pin Voltage Range

V

HV(MAX)

560 V

VDD, GATE Pin Voltage Range

V

MV(MAX)

-0.3 to 30

V

COMV, PF, BIAS, VS, CS Pin Voltage Range

V

LV(MAX)

-0.3 to 6

V

VS, CS Pin Negative Pulse Voltage at I

LV

< 0.2 A and t

PULSE

< 300 ns

V

LV(PULSE)

-1.5 V

Maximum Power Dissipation (T

A

< 50°C)

P

D(MAX)

663

mW

Maximum Junction Temperature

T

J(max)

150

°C

Storage Temperature Range T

STG

-55 to 150 °C

Junction-to-Ambient Thermal Impedance

R

θJA

158

°C/W

Junction-to-Case Thermal Impedance

R

θJC

39

°C/W

ESD Capability, Human Body Model (Note 3)

ESD

HBM

2 kV

ESD Capability, Charged Device Model (Note 3)

ESD

CDM

2 kV

Rating Symbol Min Max Unit

Ambient Temperature

T

A

-40

125

°C

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ELECTRICAL CHARACTERISTICS

V

DD

= 18 V and T

J

= -40 ~ 125°C unless otherwise specified

Parameter Test Conditions Symbol Min Typ Max Unit

VDD Section

Turn-On Threshold Voltage V

DD-ON

14.5 16.0 17.5 V

Turn-Off Threshold Voltage V

DD-OFF

6.75 7.75 8.75 V

Operating Current C

LOAD

= 1 nF, V

DD

= 18V I

DD-OP

3 5 6.5 mA

Operating Current during Auto Restart I

DD-AR

0.3 1 mA

V

DD

Over-Voltage-Protection V

DD-OVP

24 25 26 V

V

BIAS

Voltage V

BIAS

4.85 5.00 5.15 V

GATE Section

Output Voltage Low V

OL

0.2 V

Output Voltage High V

DD

= 18 V V

OH

17.8 V

Peak Sourcing Current

Design guaranteed

C

LOAD

= 1 nF, V

DD

= 20 V

C

LOAD

= 1 nF, V

DD

= 23 V

I

source

180

210

mA

Peak Sinking Current

Design guaranteed

C

LOAD

= 1 nF, V

DD

= 20 V

C

LOAD

= 1 nF, V

DD

= 23 V

I

sink

385

435

mA

Rising Time C

LOAD

= 1 nF t

r

110 150 190 ns

Falling Time C

LOAD

= 1 nF t

f

40 60 80 ns

HV Section

Supply Current From HV Pin V

HV

= 560 V, V

DD

= 0 V I

HV

3 9 mA

Leakage Current after Startup I

HV-LC

1 10 μA

JFET Regulation Time at Startup Design guaranteed t

R-JFET

400 500 600 ms

V

DD

High Limit during JFET Regulation V

DD-JFET-HL

17.5 19.0 20.5 V

V

DD

Low Limit during JFET Regulation V

DD-JFET-LL

15.5 17.0 18.5 V

PWM Section

Min. Turn-on Time Min. Limit Design guaranteed T

ON-MIN-MIN

0.40 μs

Min. Turn-on Time Max. Limit Design guaranteed T

ON-MIN-MAX

2.0 μs

Max. Turn-on Time Design guaranteed T

ON-MAX

23.3 μs

Oscillator Section

Max. Frequency f

MAX

60 65 70 kHz

Min. Frequency f

MIN

0.72 0.80 0.88 kHz

Current Sense Section

Leading-Edge Blanking Time Design guaranteed t

LEB

300 ns

Propagation Delay to GATE Design guaranteed t

PD

50 100 150 ns

Voltage Sense Section

t

DIS

Blanking Time at VS Sampling Design guaranteed t

DIS-BNK

0.95 1.00 1.05 μs

VS Clamping Voltage

I

VS

=1 mA

I

VS

=10 µA

V

VS-CLAMP

-0.1

0.35

V

Feedback Section

Reference voltage V

REF

3.465 3.5 3.535 V

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6

ELECTRICAL CHARACTERISTICS

(CONTINUED)

V

DD

= 18 V and T

J

= -40 ~ 125°C unless otherwise specified

Parameter Test Conditions Symbol Min Typ Max Unit

CV Regulation Tolerance

V

VS

= 3.5 V, T

J

= 25 °C

V

VS

= 3.5 V, T

J

= -40~125 °C

CV

REGULATION

-0.7

-1.2

+0.7

+1.2

%

Transconductance g

M

16 20 24 μmho

COMV Sink Current V

VS

= 4 V I

COMV-SINK

8 10 12 μA

COMV Source Current V

VS

= 3 V I

COMV-SOURCE

8 10 12 μA

COMV High Voltage V

COMV-HGH

4.7 V

COMV Low Voltage V

COMV-LOW

0.1 V

Start Sequence Section

Soft Start Time Design guaranteed t

SOFT-START

25.6 ms

SS1 Minimum Time Design guaranteed t

SS1-MIN

2 ms

SS1 Maximum Time Design guaranteed t

SS1-MAX

100 ms

SS21 Time Design guaranteed t

SS21

45 ms

SS22 Maximum Time Design guaranteed t

SS22

30 ms

Dynamic Section

DYN Reference Set Threshold V

DYN-REF-SET

0.72 0.80 0.88 V

DYN Reference Set Time Design guaranteed t

DYN-REF-SET

5 μs

OV Reference 5 Design guaranteed V

OV-REF5

+20 %

OV Reference 4 V

OV-REF4

+14 +15 +16 %

OV Reference 3 V

OV-REF3

+9 +10 +11 %

OV Reference 2 V

OV-REF2

+4.7 +5.7 +6.7 %

OV Reference 1 V

OV-REF1

+1.86 +2.86 +3.86 %

UV Reference 1 V

UV-REF1

-3.86 -2.86 -1.86 %

UV Reference 2 V

UV-REF2

-6.7 -5.7 -4.7 %

UV Reference 3 Design guaranteed V

UV-REF3

-10 %

Protection Section

Auto Restart Delay Time Design guaranteed t

AR

3 s

VS Ouptut Short Hys. Voltage 'H' V

VS-OS-H

0.85 0.90 0.95 V

VS Ouptut Short Hys. Voltage 'L'

V

VS-OS-L

0.65

0.70

0.75 V

OSP Delay Time Design guaranteed t

OSP-DELAY

35 ms

High Current Limit Threshold V

CS-HIGH-CL

1.13 1.20 1.27 V

Low Current Limit Threshold V

CS-LOW-CL

0.15 0.20 0.25 V

Over Current Protection Voltage V

CS-OCP

1.8 V

CS Threshold Voltage for SRSP V

CS-SRSP

0.040 0.075 0.125 V

Max. Turn-on Time for SRSP

I

VS

= 100 uA

I

VS

= 700 uA

t

TON-MAX-SRSP

7.5

1.3

10.0

1.6

12.5

1.9

μs

Threshold Temperature for OTP Design guaranteed T

OTP

150

o

C

Junction Temperature Hysteresis Design guaranteed T

OTP-HYS

30

o

C

FL7740MX

FL7740MX

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