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CY2DL814SXIT

P1-P3P4-P6P7-P8
1:4 Clock Fanout Buffe
r
ComLink™ Series
CY2DL814
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07057 Rev. *B Revised June 20, 2005
Features
• Low-voltage operation
•V
DD
= 3.3V
• 1:4 Fanout
• Single-input configurable for
— LVDS, LVPECL, or LVTTL
— Four differential pairs of LVDS outputs
• Drives 50- or 100-ohm load (selectable)
• Low input capacitance
• 85 ps typical output-to-output skew
• <4 ns typical propagation delay
• Does not exceed Bellcore 802.3 standards
• Operation at ⇒ 350 MHz – 700 Mbps
• Industrial versions available
• Packages available include TSSOP/SOIC
Description
The Cypress CY2 series of network circuits is produced using
advanced 0.35-micron CMOS technology, achieving the
industry’s fastest logic.
The Cypress CY2DL814 fanout buffer features a single
LVDS-, LVPECL-, or LVTTL-compatible input and four LVDS
output pairs.
Designed for data-communication clock management applica-
tions, the fanout from a single input reduces loading on the
input clock.
The CY2DL814 is ideal for both level translations from single
ended to LVDS and/or for the distribution of LVDS-based clock
signals. The Cypress CY2DL814 has configurable input and
output functions. The input can be selectable for
LVPECL/LVTTL or LVDS signals while the output driver’s
support standard and high drive LVDS. Drive either a 50-ohm
or 100-ohm line with a single part number/device.
Block Diagram
Pin Configuration
OUTPUT
IN+
IN-
Q1A
Q1B
Q2A
Q2B
Q4A
Q4B
Q3A
Q3B
CNTRL
LVDS /
LVPECL /
LVTTL
CONFIG
EN1
EN2
LVDS
CY2DL814
16-pin TSSOP/SOIC
EN1
CONFIG
CNTRL
VDD
IN+
IN-
EN2
GND
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
1
2
3
4
5
6
7
8
10
9
11
12
13
14
15
16
ComLink™ Series
CY2DL814
Document #: 38-07057 Rev. *B Page 2 of 8
Maximum Ratings
[1, 2]
Storage Temperature: ................................–65°C to + 150°C
Ambient Temperature:...................................–40°C to +85°C
Supply Voltage to Ground Potential
(Inputs and V
CC
only)....................................... –0.3V to 4.6V
Supply Voltage to Ground Potential
(Outputs only)........................................ –0.3V to V
DD
+ 0.3V
DC Input Voltage ................................... –0.3V to V
DD
+ 0.3V
DC Output Voltage................................. –0.3V to V
DD
+ 0.9V
Power Dissipation........................................................ 0.75W
Notes:
1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Pin Description
Pin Number Pin Name Pin Standard Interface Description
6,7 IN+, IN– Configurable Differential input pair or single line.
LVPECL default. See config below.
3 CNTRL LVTTL/LVCMOS Converts into a High drive driver from a standard LVDS.
Standard drive (logic = 0)
B/High drive/Bus (logic = 1)
2 CONFIG LVTTL/LVCMOS Converts inputs (IN
+
/IN
–
), (EN, EN#) from the default
LVPECL/LVDS (logic = 0)
To LVTTL/LVCMOS (logic = 1)
1,8 EN1, EN2 LVTTL/LVCMOS Enable/disable logic. See Table 1 below for details.
16,15,14,13
12,11,10,9
Q1A, Q1B, Q2A,
Q2B,
Q3A, Q3B, Q4A,
Q4B
LDVS Differential outputs.
4V
DD
POWER Positive supply voltage
5
G
ND
POWER Ground
Table 1. EN1 EN2 Function Table–Differential Input Mode
Enable Logic Input Outputs
EN1 EN2 IN+ IN– QnA QnB
HXHLHL
HXLHLH
XLHLHL
XLLHLH
LHXXZZ
Table 2. Output Drive Control for Standard and Bus/B/High Drive B
CNTRL Pin 3 Binary Value Drive STD Impedance Output Voltage Value
0 Standard 100 ohm V0 = Voutput
50 ohm V = 1/2 * V0
1 High Drive/Bus/B 100 ohm V = 2 * V0
50 ohm V = V0
ComLink™ Series
CY2DL814
Document #: 38-07057 Rev. *B Page 3 of 8
Table 3. Input Receiver Configuration for Differential or LVTTL/LVCMOS
CONFIG
Pin 2
Binary Value Input Receiver Family Input Receiver Type
1 LVTTL in LVCMOS Single-ended, Non-inverting, Inverting, Void of Bias Resistors
0 LVDS Low-voltage Differential Signaling
LVPECL Low-voltage Pseudo (Positive) Emitter Coupled Logic
Table 4. Function Control of the TTL Input Logic Used to Accept or Invert the Input Signal
LVTTL/LVCMOS Input Logic
Input Condition Input Logic Output Logic Q Pins, Q1A or Q1
Ground IN– Pin 7
IN+ Pin 6 Input True
V
CC
IN– Pin 7
IN+ Pin 6 Input Invert
Ground IN+ Pin 6
IN– Pin 7 Input True
V
CC
IN+ Pin 6
IN– Pin 7 Input Invert
Table 5. Power Supply Characteristics
Parameter Description Test Conditions Min. Typ. Max. Unit
I
CCD
Dynamic Power Supply Current V
DD
= Max.
Input toggling 50% Duty Cycle,
Outputs Open
1.5 2.0 mA/MHz
I
C
Total Power Supply Current V
DD
= Max.
Input toggling 50% Duty Cycle,
Outputs Open
fL=100 MHz
90 100 mA
Table 6. D.C Electrical Characteristics: 3.3V–LVDS Input
Parameter Description Conditions Min. Typ. Max. Unit
V
ID
Magnitude of Differential Input Voltage 100 600 mV
V
IC
Common-mode of Differential Input Voltage IV
ID
I (min. and max.) IVIDI/2 2.4–(IVIDI/2) V
V
IH
Input High Voltage Guaranteed Logic High Level Config/Cntrl Pins 2 V
V
IL
Input Low Voltage Guaranteed Logic Low Level 0.8 V
I
IH
Input High Current V
DD
= Max. V
IN
= V
DD
±10 ±20 µA
I
IL
Input Low Current V
DD
= Max. V
IN
= V
SS
±10 ±20 µA
I
I
Input High Current V
DD
= Max., V
IN
= V
DD
(max.) ±20 µA
Table 7. D.C Electrical Characteristics: 3.3V–LVPECL Input
Parameter Description Conditions Min. Typ. Max. Unit
V
ID
Differential Input Voltage p-p Guaranteed Logic High Level 400 2600 mV
V
CM
Common-mode Voltage 1.65 2.25 V
I
IH
Input High Current V
DD
= Max. V
IN
= V
DD
±10 ±20 µA
I
IL
Input Low Current V
DD
= Max. V
IN
= V
SS
±10 ±20 µA
I
I
Input High Current V
DD
= Max., V
IN
= V
DD
(Max.) ±20 µA
P1-P3P4-P6P7-P8

CY2DL814SXIT

Mfr. #:
Buy CY2DL814SXIT
Manufacturer:
Cypress Semiconductor
Description:
Clock Buffer 3.3V 400MHz LVDS Buffer
Lifecycle:
New from this manufacturer.
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