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PL123E-09HSC

P1-P3P4-P6P7-P9P10-P10
(Preliminary) PL123E-09
Low Skew Zero Delay Buffer
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 1
FEATURES
Frequency Range 10MHz to 220MHz
Zero input - output delay.
Low Output to Output Skew
Optional Drive Strength:
Standard (8mA) PL123E-09
High (12mA) PL123E-09H
2.5V or 3.3V, ±10% operation.
Available in 16-Pin SOP or TSSOP packages
DESCRIPTION
The PL123E-09 (-09H for High Drive) is a high perfor-
mance, low skew, low jitter zero delay buffer d esigned
to distribute high speed clocks. It has two low-skew
output banks, of 4 outputs each, that are synchronized
with the input. Control of the two banks o f outputs is
achieved by using the S1 and S2 inputs as shown in
the Selector Definition table on page 2.
The synchronization is established via CLKOUT feed
back to the input of the PLL. Since the skew between
the input and output is less than 100ps, the device
acts as a zero delay buffer. The input output propaga-
tion delay can be advanced or delayed by adjusting the
load on the CLKOUT pin.
These parts are not intended for 5V input-tolerant ap-
plications.
BLOCK DIAGRAM
PLL
REF CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
Selector
Inputs
Mux
CLKB1
CLKB2
CLKB3
CLKB4
S1
S2
1REF
CLKA1
CLKA2
VDD
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
10
11
12
13
14
15
16
98
7
6
5
4
3
2
S2
CLKB2
CLKB1
GND
Bank B Bank A
(Preliminary) PL123E-09
Low Skew Zero Delay Buffer
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 2
PIN DESCRIPTIONS
Name
Package Type
Type
Description
TSSOP-16L
SOP-16L
REF
[1 ]
1
1
I
Input reference frequency.
CLKA1
[2 ]
2
2
O
Buffered clock output, Bank A
CLKA2
[2 ]
3
3
O
Buffered clock output, Bank A
VDD
4,13
4,13
P
VDD connection
GND
5,12
5,12
P
GND connection
CLKB1
[2 ]
6
6
O
Buffered clock output, Bank B
CLKB2
[2 ]
7
7
O
Buffered clock output, Bank B
S2
[3 ]
8
8
I
Selector input
S1
[3 ]
9
9
I
Selector input
CLKB3
[2 ]
10
10
O
Buffered clock output, Bank B
CLKB4
[2 ]
11
11
O
Buffered clock output, Bank B
CLKA3
[2 ]
14
14
O
Buffered clock output, Bank A
CLKA4
[2 ]
15
15
O
Buffered clock output, Bank A
CLKOUT
[2 ]
16
16
O
Buffered clock output. Internal feedback on this pin.
Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. 3: Weak Pull-Up on S1 and S2
SELECTOR DEFINITION
S2
CLOCK A1–A4
(Bank A)
CLOCK B1–B4
(Bank B)
CLKOUT
Output Source
PLL Shutdown
0
Three-state
Three-state
Driven
PLL
N
0
Driven
Three-state
Driven
PLL
N
1
Driven
Driven
Driven
Reference
Y
1
Driven
Driven
Driven
PLL
N
INPUT / OUTPUT SKEW CONTROL
The PL123E-09 will achieve Zero Delay from input to output when all the outputs are loaded equally . Adjust-
ments to the input/output delay can be made by adding additional loading to the CLKOUT pin.
Please contact Micrel for more information.
(Preliminary) PL123E-09
Low Skew Zero Delay Buffer
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 3
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination
Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this equals
ringing!
- Long trace = Transmission Line. Without proper termi-
nation this will cause reflections ( looks like ringing ).
- Design long traces as “striplines” or “microstrips” with
defined impedance.
- Match trace at one side to avoid reflections bouncing
back and forth.
Decoupling and Power Supply
Considerations
- Place decoupling capacitors as close as possible to
the VDD pin(s) to limit noise from the power supply
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency depend-
ant. Typical values to use are 0.1F for designs
using frequencies < 50MHz and 0.01F for designs
using frequencies > 50MHz.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
( Typical buffer impedance 20 
To CMOS Input
50 line
Connect a 33 series
resistor at each of the output
clocks to enhance the
stability of the output signal
P1-P3P4-P6P7-P9P10-P10

PL123E-09HSC

Mfr. #:
Buy PL123E-09HSC
Manufacturer:
Microchip Technology / Micrel
Description:
Clock Buffer Low Skew 1:9 Zero Delay Buffer
Lifecycle:
New from this manufacturer.
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