NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
Recommended Substitutions:
8-Bit Addressable, DMOS Power Driver
A6A259
Date of status change: October 29, 2007
These parts are no longer in production The device should not be
purchased for new design applications. Samples are no longer available.
Discontinued Product
Data Sheet
26186.121
8-BIT ADDRESSABLE
DMOS POWER DRIVER
The A6A259KA and A6A259KLB combine a 3-to-8 line CMOS
decoder and accompanying data latches, control circuitry, and DMOS
outputs in a multi-functional power driver capable of storing single-line
data in the addressable latches or use as a decoder or demuliplexer.
Driver applications include relays, solenoids, and other medium-current
or high-voltage peripheral power loads.
The CMOS inputs and latches allow direct interfacing with micro-
processor-based systems. Use with TTL may require appropriate pull-
up resistors to ensure an input logic high. Four modes of operation are
selectable with the CLEAR and ENABLE inputs.
The addressed DMOS output inverts the DATA input with all
unaddressed outputs remaining in their previous states. All of the output
drivers are disabled (the DMOS sink drivers turned off) with the
CLEAR input low and the ENABLE input high. The A6A259KA/KLB
DMOS open-drain outputs are capable of sinking up to 500 mA.
The A6A259KA is furnished in a 20-pin dual in-line plastic pack-
age. The A6A259KLB is furnished in a 24-lead wide-body, small-
outline plastic batwing package (SOIC) with gull-wing leads for surface-
mount applications. Copper lead frames, reduced supply current re-
quirements, and low on-state resistance allow both devices to sink 150
mA from all outputs continuously, to ambient temperatures over 85°C.
FEATURES
50 V Minimum Output Clamp Voltage
350 mA Output Current (all outputs simultaneously)
1 Typical
r
DS(on)
Internal Short-Circuit Protection
Low Power Consumption
Replacements for TPIC6A259N and TPIC6A259DW
6A259
PRELIMINARY INFORMATION
(Subject to change without notice)
March 24, 2003
LOGIC
GROUND
S
1
OUT
3
V
DD
POWER
GROUND
CLEAR
Dwg. PP-050-4
OUT
2
POWER
GROUND
ENABLE EN
POWER
GROUND
S
2
(MSB)
OUT
5
OUT
4
POWER
GROUND
OUT
0
OUT
1
S
0
(LSB)
LOGIC
SUPPLY
OUT
6
OUT
7
DATA
DECODER
LATCHES
13
14
15
16
17
19
12
18
20
11
1
2
3
8
9
4
5
6
7
10
ABSOLUTE MAXIMUM RATINGS
at T
A
= 25°C
Output Voltage, V
O
............................ 50 V
Output Drain Current,
Continuous, I
O
...................... 350 mA*
Peak, I
OM
........................... 1100 mA*†
Peak, I
OM
.................................... 2.0 A†
Single-Pulse Avalanche Energy,
E
AS
............................................. 75 mJ
Logic Supply Voltage, V
DD
.............. 7.0 V
Input Voltage Range,
V
I
............................... -0.3 V to +7.0 V
Package Power Dissipation,
P
D
....................................... See Graph
Operating Temperature Range,
T
A
............................. -40°C to +125°C
Storage Temperature Range,
T
S
............................. -55°C to +150°C
*Each output, all outputs on.
† Pulse duration 100 µs, duty cycle 2%.
Caution: These CMOS devices have input static
protection (Class 3) but are still susceptible to dam-
age if exposed to extremely high static electrical
charges.
Always order by complete part number:
Part Number Package R
θθ
θθ
θJA
R
θθ
θθ
θJC
R
θθ
θθ
θJT
A6A259KA 20-pin DIP 55°C/W 25°C/W
A6A259KLB 24-lead SOIC 55°C/W 6°C/W
A6A259KA (DIP)
6A259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
2
Copyright © 2003 Allegro MicroSystems, Inc.
FUNCTION TABLE
Inputs
Addressed Other
CLEAR ENABLE DATA OUTPUT OUTPUTs Function
HLH L R
Addressable
HLL H R
Latch
H H X R R Memory
LLH L H
8-Line
LLL H H
Demultiplexer
L H X H H Clear
L = Low Logic Level H = High Logic Level X = Irrelevant R = Previous State
LATCH SELECTION TABLE
Select Inputs
Addressed
S
2
(MSB)S
1
S
0
(LSB) OUTPUT
LLL 0
LLH 1
LHL 2
LHH 3
HLL 4
HLH 5
HHL 6
HHH 7
DMOS POWER DRIVER OUTPUTLOGIC INPUTS
Dw
g
. EP-063-5
OUT
IN
Dwg. EP-010-15
V
DD
A6A259KLB (SOIC)
POWER
GROUND
CLEAR
POWER
GROUND
ENABLE EN
POWER
GROUND
S
2
(MSB)
OUT
5
OUT
4
POWER
GROUND
OUT
6
OUT
7
DATA
LOGIC
GROUND
S
1
OUT
3
V
DD
POWER
GROUND
OUT
2
POWER
GROUND
POWER
GROUND
POWER
GROUND
OUT
0
OUT
1
S
0
(LSB)
LOGIC
SUPPLY
DECODER
LATCHES
Dwg. PP-050-3A
1
2
3
817
18
19
20
21
23
4
5
6
7
22
24
12
9
10
11
13
14
15
16
50 75 100 125 150
5
1
0
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
TEMPERATURE IN °°
°°
C
4
3
2
25
Dwg. GP-049-5
SUFFIX 'LB', R = 6.0°C/W
θJT
R = 55°C/W
θJA
SUFFIX 'A', R = 25°C/W
θJC

A6A259KLBTR

Mfr. #:
Manufacturer:
Description:
IC PWR DRVR 8BIT ADDRESS 24SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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