MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
______________________________________________________________________________________ 15
ing edge of the first clock cycle after conversion end
(when BUSY goes high). As mentioned previously, two
more read operations (after BUSY goes high) are
needed to access the conversion results. The only dif-
ference is that now the low byte can be read first. This
happens by allowing the first read operation to occur
with HBEN low, where the 8 LSBs are accessed. The
second read, with HBEN high, accesses the 4 MSBs
with 4 leading 0s.
Serial-Interface Mode
The serial mode is compatible with Microwire, SPI and
QSPI serial interfaces. In addition, a framing signal
(SSTRB) is provided that allows the devices to interface
with the TMS320 family of DSPs. Set PAR low for serial
mode. A falling edge on CS causes the T/H to sample
the input (Figure 10). Conversion always begins on the
next falling edge of SCLK, regardless of where CS
occurs. The DOUT line remains high-impedance until a
conversion begins. During the MSB decision, DOUT
remains low (leading 0), while SSTRB goes high to indi-
cate that a data frame is beginning. The data is avail-
able at DOUT on the rising edge of SCLK (SCLK
OUT
when using an internal clock) and transitions on the
falling edge. DOUT remains low after all data bits have
been shifted out, inserting trailing 0s in the data stream
until CS returns high. The SCLK
OUT
signal is synchro-
nous with the internal or external clock.
For interface flexibility, DOUT, SCLK
OUT
and SSTRB
signals enter a high-impedance state when CS is high.
When CS is low, RD controls the status of SCLK
OUT
and
SSTRB outputs. A logic low RD enables SCLK
OUT
and
SSTRB, while a logic high forces both outputs into a
high-impedance state. Also, with CS low and HBEN
high, SCLK
OUT
drives continuously, regardless of con-
version status. This is useful with µPs that require a
continuous serial clock. If CS and HBEN are low,
SCLK
OUT
is output only during the conversion cycle,
while the converter internal clock runs continuously.
This is useful for creating a simple serial-to-parallel
interface without shift-register overflow (Figure 11).
Maximum Clock Rate in Serial Mode
The maximum SCLK rate depends on the minimum
setup time required at the serial data input to the µP
and the ADC’s DOUT to SCLK delay (t
22
) (see Figure
12). The maximum f
SCLK
is as follows:
