various interface modes.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. Acquisition time is cal-
culated by: t
ACQ
= 10(R
S
+ R
IN
)C
HOLD
(but never less
than 2µs), where R
IN
= 2kΩ, R
S
= source impedance of
the input signal, and C
HOLD
= 32pF (see Figure 4).
Input Bandwidth
The ADC’s input tracking circuitry has a 1MHz typical
large-signal bandwidth characteristic, and a 30V/µs
slew rate. It is possible to digitize high-speed transients
and measure periodic signals with bandwidths exceed-
ing the ADC’s sample rate of 100ksps by using under-
sampling techniques. Note that if undersampling is
used to measure high-frequency signals, special care
must be taken to avoid aliasing errors. Without ade-
quate input bandpass filtering, out-of-band signals and
noise may be aliased into the measurement band.
Input Protection
Internal protection diodes, which clamp the analog input
to V
DD
and V
SS
, allow AIN+ to swing from (V
SS
- 0.3V) to
(V
DD
+ 0.3V) with no risk of damage to the ADC.
However, for accurate conversions near full scale, AIN+
should not exceed the power supplies by more than
50mV because ADC accuracy is affected when the pro-
tection diodes are even slightly forward biased.
Digital Interface
Starting a Conversion
In parallel mode, the ADC is controlled by the CS, RD,
and HBEN inputs, as shown in Figure 6. The T/H
enters hold mode and a conversion starts at the falling
edge of CS and RD while HBEN (not shown) is low.
BUSY goes low as soon as the conversion starts. On
the falling edge of the 13th input clock pulse after the
conversion starts, BUSY goes high and the conversion
result is latched into three-state output buffers. In seri-
al mode, the falling edge of CS initiates a conversion,
and the T/H enters hold mode. Data is shifted out seri-
ally as the conversion proceeds (Figure 10). See the
Parallel Digital-Interface Mode
and
Serial-Interface
Mode
sections for details.
Internal/External Clock
Figure 5 shows the MAX191 clock circuitry. The ADC
includes internal circuitry to generate a clock with an
external capacitor. As indicated in the
Typical
Operating Characteristics
, a 120pF capacitor con-
nected between the CLK and DGND pins generates
a 1MHz nominal clock frequency (Figure 5).
Alternatively, an external clock (between 100kHz and
1.6MHz) can be applied to CLK. When using an exter-
nal clock source, acceptable clock duty cycles are
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
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