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RT8106AGQW

P1-P3P4-P6P7-P9P10-P12P13-P14
10
RT8106/A
www.richtek.com
DS8106/A-04 April 2011
The ESR zero is contributed by the ESR associated with
the output capacitance. Note that this requires that the
output capacitor should have enough ESR to satisfy
stability requirements. The ESR zero of the output
capacitor is expressed as follows :
ESRC2
1
f
OUT
ESR
××
=
π
2) Compensation Frequency Equations
The compensation network consists of the error amplifier
and the impedance networks Z
C
and Z
F
as shown in Figure
4.
Figure 4. Compensation Loop
C2 x R2 x 2
1
f
Z1
π
=
C2C1
C2 x C1
x R2 x 2
1
f
P1
+
=
π
Figure 5. shows the DC-DC converter's magnitude Bode
Plot. The compensation gain uses external impedance
networks Z
C
and Z
F
to provide a stable, high bandwidth
loop. High crossover frequency is desirable for fast
transient response, but it often jeopardize the system
stability. In order to cancel one of the LC filter poles, place
the zero before the LC filter resonant frequency. In the
experience, place the zero at 75% of the LC filter resonant
frequency. Crossover frequency should be higher than the
ESR zero but less than 1/5 of the switching frequency.
The second pole is placed at half the switching frequency.
Figure 5. Bode Plot
Frequency
10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz
vdb(vo) vdb(comp2) vdb(lo)
-40
0
40
80
-60
10 100 1k 10k 100k 1M
80
40
0
20
60
-20
-40
-60
Loop Gain
Compensation
Gain
Modulator
Gain
Frequency (Hz)
Gain (dB)
Component Selection
1) Inductor Selection
The selection of output inductor is based on the
considerations of efficiency, output power and operating
frequency. Low inductance value has smaller size, but
results in low efficiency, large ripple current and high output
ripple voltage. Generally, an inductor that limits the ripple
current (ΔI
L
) between 20% and 50% of output current is
appropriate. Figure 6. shows the typical topology of the
synchronous step-down converter and its related
waveforms.
+
S1
S2
V
IN
i
S1
i
S2
I
OUT
V
OUT
+
-
R
L
r
C
C
OUT
i
C
V
OR
+
-
V
OC
+
-
V
L
+
-
L
I
L
1) Modulator Frequency Equations
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
COMP
(output voltage over the error
amplifier output). This transfer function is dominated by a
DC gain, a double pole, and an ESR zero as shown in
Figure 3. The DC gain of the modulator is the input voltage
(V
IN
) divided by the peak to peak oscillator voltage V
OSC
.
The output LC filter introduces a double pole, 40dB/decade
gain slope above its corner resonant frequency, and a total
phase lag of 180 degrees. The resonant frequency of the
LC filter is expressed as :
OUTOUT
LC
CL2
1
f
×
=
π
+
-
FB
V
REF
COMP
EA
Z
C
Z
F
C1
C2
R2
R1
V
OUT
11
RT8106/A
DS8106/A-04 April 2011
www.richtek.com
V
L
V
IN
- V
OUT
- V
OUT
i
L
I
L
= I
OUT
ΔI
L
i
S1
i
S2
T
S
T
ON
T
OFF
V
g1
V
g2
Figure 6. The Waveforms of Synchronous Step-Down
Converter
OUT
L
IN OUT
IN
OUT
IN OUT
IN L
V
ΔI
D
VV L ; Δt; D
ΔtfsV
V
L(V V )
VfsΔI
−= = =
=− ×
××
According to Figure 6. the ripple current of inductor can
be calculated as follows :
(1)
Where :
V
IN
= Maximum input voltage
V
OUT
= Output Voltage
Δt = S1 turn on time
ΔI
L
= Inductor current ripple
f
S
= Switching frequency
D = Duty Cycle
r
C
= Equivalent series resistor of output capacitor
L
dt
=
dt
L
V
OUT
=
V
OR
i
L
i
C
di
L
ΔI
L
1/2
0
0
ΔI
L
x r
c
V
OC
t1 t2
ΔV
OC
ΔI
L
V
IN
-V
OUT
T
S
I
OUT
di
L
Figure 7. The Related Waveforms of Output Capacitor
2) Output Capacitor Selection
The selection of output capacitor depends on the output
ripple voltage requirement. Practically, the output ripple
voltage is a function of both capacitance value and the
equivalent series resistance (ESR) r
C
. Figure 7. shows
the related waveforms of output capacitor.
The AC impedance of output capacitor at operating
frequency is quite smaller than the load impedance, so
the ripple current (ΔI
L
) of the inductor current flows mainly
through the output capacitor. The output ripple voltage is
described as :
t2
t1
OUT OR OC
OUT L C
O
2
OUT
OUT L L
S
OL
ΔV ΔV ΔV
1
ΔV ΔIrc i dt
C
1V
ΔV ΔI ΔIrc (1D)T
8C
=+
=×+
=××+ −
∫
where ΔV
OR
is caused by ESR and ΔV
OC
by capacitance.
For electrolytic capacitor application, typically 90% to 95%
of the output voltage ripple is contributed by the ESR of
the output capacitor. So Equation (4) can be simplified
as: ΔV
OUT
= ΔI
L
x r
C
(2)
(3)
(4)
(5)
12
RT8106/A
www.richtek.com
DS8106/A-04 April 2011
Users can connect capacitors in parallel to get calculated
ESR.
Input Capacitor
The selection of input capacitor is mainly based on its
maximum ripple current capability. The buck converter
draws pulsewise current from the input capacitor during
the on time of the S1 as shown in Figure 6. The RMS
value of ripple current flowing through the input capacitor
is described as :
(A) D)D(1IIrms
OUT
−=
(6)
The input capacitor must be cable of handling this ripple
current. Sometime, for higher efficiency, the low ESR
capacitor is necessary.
PCB Layout Considerations
MOSFETs switch very fast and efficiently. The current
transition speed between different derices causes voltage
spikes across the interconnecting impedances and
parasitic circuit elements. The voltage spikes can degrade
efficiency and radiate noise that results in over-voltage
stress on devices. Careful component placement layout
and printed circuit design can minimize the voltage spikes
induced in the converter. For example, during the period
of upper MOSFETs turn-off transition, the upper MOSFET
was carrying the full load current. During turn-off, current
stops flowing in the upper MOSFET and is picked up by
the low side MOSFET or schottky diode. Any inductance
in the switched current path generates a large voltage
spike during the switching interval. Careful component
selections, layout of the critical components, and use
shorter and wider PCB traces help in minimizing the
magnitude of voltage spikes. The RT8106/A DC-DC
converter integrates two sets of critical components just
as follows. The switching power components are most
critical because they switch large amounts of energy, and
as such, they tend to generate equally large amounts of
noise. The critical small signal components are those
connected to sensitive nodes or those supplying critical
bypass current.
For the proper layout of the RT8106/A the power
components and the PWM controller should be placed
firstly. And than place the input capacitors, especially the
high-frequency ceramic decoupling capacitors, close to
the power switches. Place the output inductor and output
capacitors between the MOSFETs and the load. Also
locate the PWM controller near by the MOSFETs. A multi-
layer printed circuit board is recommended. Figure 8
shows the connections of the critical components in the
converter.
Note that the capacitors C
IN
and C
OUT
each of them
represents numerous physical capacitors. Use a dedicated
grounding plane and use vias to ground all critical
components to this layer. Apply another solid layer as a
power plane and cut this plane into smaller islands of
common voltage levels. The power plane should support
the input power and output power nodes. Use copper filled
polygons on the top and bottom circuit layers for the LX
node, but it is not necessary to oversize this particular
island. Since the LX node is subjected to very high dV/dt
voltages, the stray capacitance formed between these
islands and the surrounding circuitry will tend to couple
switching noise. Use the remaining printed circuit layers
for small signal routing. The PCB traces between the PWM
controller and the gate of MOSFET and also the traces
connecting source of MOSFETs should be sized to carry
2A peak currents.
Figure 8. The Connections of the Critical Components in
the Converter
+
+
LOAD
+
VCC
GND
RT8106/A
FB
LGATE
UGATE
IL
IQ1
V
OUT
Q2
Q1
IQ2
5V/12V
GND
P1-P3P4-P6P7-P9P10-P12P13-P14

RT8106AGQW

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