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AS1152
Data Sheet - Applications
9 Applications
Figure 17. Typical Application Circuit
Power-Supply Bypassing
To bypass VCC, use high-frequency surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the
device as possible, with the smaller valued capacitor closest to pin VCC.
Differential Traces
Input trace characteristics can adversely affect the performance of the AS1152.
!
Use controlled-impedance PC board traces to match the cable characteristic impedance. The termination resistor is
also matched to this characteristic impedance.
!
Eliminate reflections and ensure that noise couples as common mode by running the differential traces near each
other.
!
Reduce skew by using matched trace lengths. Tight skew control is required to minimize emissions and proper data
recovery of the devices.
!
Route each channel’s differential signals very close to each other for optimal cancellation of their respective exter-
nal magnetic fields. Use a constant distance between the differential traces to avoid irregularities in differential
impedance.
!
Avoid 90° turns (use two 45° turns).
!
Minimize the number of vias to further prevent impedance irregularities.
Table 5. Function Table
Enable Pins Input Output
EN ENn INx+ INx- OUTx
H L or Open L L H
H L or Open
HHL
Other Combinations of Enable Pin Settings Don’t Care Z Z
LVDS
Signals
107Ω
107Ω
107Ω
107Ω
LVTTL/LVCMOS
Data Inputs
LVTTL/LVCMOS
Data Outputs
100Ω Shielded Twisted Cable or Microstrip PC Board Traces
Tx
Tx
Tx
Tx
Rx
Rx
Rx
Rx
AS1151
Quad LVDS Receiver
AS1152
www.austriamicrosystems.com Revision 1.00 11 - 15
AS1152
Data Sheet - Applications
Cables and Connectors
Supported transmission media include printed circuit board traces, backplanes, and cables.
!
Use cables and connectors with matched differential impedance (typically 100Ω) to minimize impedance mis-
matches.
!
Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic
field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver.
!
Avoid the use of unbalanced cables such as ribbon cable or simple coaxial cable.
Board Layout
The device should be placed as close to the interface connector as possible to minimize LVDS trace length.
!
Keep the LVDS and any other digital signals separated from each other to reduce crosstalk.
!
Use a four-layer PC board that provides separate power, ground, LVDS signals, and input signals.
!
Isolate the input LVDS signals from each other and the output LVCMOS/LVTTL signals from each other to prevent
coupling.
!
Separate the input LVDS signals from the output signals planes with the power and ground planes for best results.
Figure 18. Driver Propagation Delay and Transition Time Waveforms
Figure 19. Driver Propagation Delay and Transition Time Test Circuit
tTHLtTLH
tPLHD
tPHLD
0 Differential
1.5V
20%
80%
0
20%
OUTx-
OUTx+
INx
VOH
VOL
0
1.5V
VDIFF = (VOUTx+) - (VOUTx-)
80%
0
OUTx-
Generator
50Ω
R
L
OUTx+
INx
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AS1152
Data Sheet - Applications
Figure 20. Driver VOD and VOS Test Circuit
Figure 21. Driver High Impedance Delay Waveforms
Figure 22. Driver High-Impedance Delay Test Circuit
VOS
VOD
OUTx+
OUTx-
RL/2
RL/2
VCC
GND
INx
1.5V
EN when ENn = 0 or Open
ENn when EN = VCC
1.5V
1.5V
1.5V
50%
50%
3V
0
VOL
VOH
1.2V
t
PZL
tPLZ
OUTx+ When INx = VCC
OUTx- When INx = 0
0
3V
tPZH
tPHZ
50%
50%
1.2V
OUTx+ When INx = 0
OUTx- When INx = V
CC
VCC
Generator
50Ω
R
L/2
ENn
EN
GND
INx
OUTx+
OUTx-
RL/2
+1.2V
1/4 AS1152

AS1152

Mfr. #:
Manufacturer:
ams
Description:
LVDS Interface IC
Lifecycle:
New from this manufacturer.
Delivery:
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