CMOS CLOCKED FIFO WITH
BUS-MATCHING AND
BYTE SWAPPING 64 x 36
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-3145/3
IDT723613
JANUARY 2009
IDT and the IDT logo are registered trademarks of Integrated Device Technology Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©
FEATURES
••
••
• Free-running CLKA and CLKB may be asynchronous or
coincident (permits simultaneous reading and writing of data on
a single clock edge)
••
••
• 64 x 36 storage capacity FIFO buffering data from Port A to
Port B
••
••
• Mailbox bypass registers in each direction
••
••
• Dynamic Port B bus sizing of 36 bits (long word), 18-bits (word),
and 9 bits (byte)
••
••
• Selection of Big- or Little-Endian format for word and byte bus
sizes
••
••
• Three modes of byte-order swapping on Port B
••
••
• Programmable Almost-Full and Almost-Empty flags
••
••
• Microprocessor interface control logic
••
••
• FF, AF flags synchronized by CLKA
••
••
• EF, AE flags synchronized by CLKB
••
••
• Passive parity checking on each Port
••
••
• Parity Generation can be selected for each Port
••
••
• Supports clock frequencies up to 67 MHz
••
••
• Fast access times of 10 ns
••
••
• Available in 132-pin quad flatpack (PQFP) or space-saving
120-pin thin quad flatpack (TQFP)
••
••
• Industrial temperature range (–40
°°
°°
°C to +85
°°
°°
°C) is available
••
••
• Green parts available, see orderng information
DESCRIPTION
The IDT723613 is a monolithic, high-speed, low-power, CMOS synchro-
nous (clocked) FIFO memory which supports clock frequencies up to 67 MHz
and has read-access times as fast as 10 ns. The 64 x 36 dual-port SRAM FIFO
buffers data from port A to port B. The FIFO has flags to indicate empty and full
conditions, and two programmable flags, Almost-Full (AF) and Almost-Empty
(AE), to indicate when a selected number of words is stored in memory. FIFO
data on port B can be output in 36-bit, 18-bit, and 9-bit formats with a choice of
big- or Little-Endian configurations. Three modes of byte-order swapping are
possible with any bus-size selection. Communication between each port can
bypass the FIFO via two 36-bit mailbox registers. Each mailbox register has
FUNCTIONAL BLOCK DIAGRAM
Mail 2
Register
Mail 1
Register
Input
Register
Output
Register
64 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
Device
Control
RST
PEFA
MBF2
Port-B
Control
Logic
MBF1
EF
AE
36
B
0
- B
35
FF
AF
FS
0
FS
1
3145 drw01
Programmable
Flag Offset
Registers
A
0
- A
35
Parity
Gen/Check
Parity
Generation
FIFO
ODD/
EVEN
PGA
Parity
Gen/Check
PGB
PEFB
36
RAM ARRAY
64 x 36
Bus-Matching and
Byte Swapping
Output
Register
CLKB
CSB
W/RB
ENB
BE
SIZ0
SIZ1
SW0
SW1
Port-B
Control
Logic
