IDT723613L15PF Datasheet IDT723613L15PF, IDT723613L15PF8 | P10-P12

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723613 CMOS CLOCKED FIFO WITH

BUS-MATCHING AND BYTE SWAPPING 64 x 36

JANUARY 14, 2009

TEMPERATURE RANGES

FUNCTIONAL DESCRIPTION

RESET (RST)

The IDT723613 is reset by taking the Reset (RST) input LOW for at least four

port A Clock (CLKA) and four port B Clock (CLKB) LOW-to-HIGH transitions.

The Reset input can switch asynchronously to the clocks. A device reset

initializes the internal read and write pointers of the FIFO and forces the Full Flag

(FF) LOW, the Empty Flag (EF) LOW, the Almost-Empty flag (AE) LOW, and

the Almost-Full flag (AF) HIGH. A reset also forces the Mailbox Flags (MBF1,

MBF2) HIGH. After a reset, FF is set HIGH after two LOW-to-HIGH transitions

of CLKA. The device must be reset after power up before data is written to its

memory.

A LOW-to-HIGH transition on the RST input loads the Almost-Full and Almost-

Empty Offset register (X) with the value selected by the Flag Select (FS0, FS1)

inputs. The values that can be loaded into the register are shown in Table 1.

FIFO WRITE/READ OPERATION

The state of the port A data (A0-A35) outputs is controlled by the port-A Chip

Select (CSA) and the port-A Write/Read select (W/RA). The A0-A35 outputs are

in the high-impedance state when either CSA or W/RA is HIGH. The A0-A35

outputs are active when both CSA and W/RA are LOW.

Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH

transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is

LOW, and FFA is HIGH (see Table 2).

The state of the port B data (B0-B35) outputs is controlled by the port B Chip

Select (CSB) and the port B Write/Read select (W/RB). The B0-B35 outputs are

in the high-impedance state when either CSB or W/RB is HIGH. The B0-B35

outputs are active when both CSB and W/RB are LOW. Data is read from the

FIFO to the B0-B35 outputs by a LOW-to-HIGH transition of CLKB when CSB

CSA W/RA ENA MBA CLKA A0-A35 Outputs Port Function

H X X X X In high-impedance state None

L H L X X In high-impedance state None

LHHL↑ In high-impedance state FIFO write

LHHH↑ In high impedance state Mail1 write

L L L L X Active, mail2 register None

LLHL↑ Active, mail2 register None

L L L H X Active, mail2 register None

LLHH↑ Active, mail2 register Mail2 read (set MBF2 HIGH)

TABLE 2 — PORT A ENABLE FUNCTION TABLE

Almost-Full and

FS1 FS0 RST Almost-Empty Flag

Offset Register (X)

HH↑ 16

HL↑ 12

LH↑ 8

LL↑ 4

TABLE 1 — FLAG PROGRAMMING

is LOW, W/RB is LOW, ENB is HIGH, EFB is HIGH, and either SIZ0 or SIZ1

is LOW (see Table 3).

The setup and hold-time constraints to the port clocks for the port Chip Selects

(CSA, CSB) and Write/Read selects (W/RA, W/RB) are only for enabling write

and read operations and are not related to high-impedance control of the data

outputs. If a port enable is LOW during a clock cycle, the port’s Chip Select and

Write/Read select can change states during the setup and hold time window of

the cycle.

SYNCHRONIZED FIFO FLAGS

Each FIFO flag is synchronized to its port clock through two flip-flop stages.

This is done to improve the flags’ reliability by reducing the probability of

metastable events on their outputs when CLKA and CLKB operate asynchro-

nously to one another. FF and AF are synchronized to CLKA. EF and AE are

synchronized to CLKB. Table 4 shows the relationship of each port flag to the

level of FIFO fill.

EMPTY FLAG (EF)

The FIFO Empty Flag is synchronized to the port clock that reads data from

its array (CLKB). When the EF is HIGH, new data can be read to the FIFO output

are ignored. When reading the FIFO with a byte or word size on port B, EF is

set LOW when the fourth byte or second word of the last long word is read.

The FIFO read pointer is incremented each time a new word is clocked to

its output register. The state machine that controls the EF monitors a write-pointer

and read-pointer comparator that indicates when the FIFO SRAM status is

empty, empty+1, or empty+2. A word written to the FIFO can be read to the

FIFO output register in a minimum of three port B clock (CLKB) cycles.

Therefore, an EF is LOW if a word in memory is the next data to be sent to the

FIFO output register and two CLKB cycles have not elapsed since the time the

word was written. The EF of the FIFO is set HIGH by the second LOW-to-HIGH

transition of CLKB, and the new data word can be read to the FIFO output register

in the following cycle.

A LOW-to-HIGH transition on CLKB begins the first synchronization cycle of

a write if the clock transition occurs at time tSKEW1 or greater after the write.

Otherwise, the subsequent CLKB cycle can be the first synchronization cycle

(see Figure 10).

FULL FLAG (FF)

The FIFO Full Flag is synchronized to the port clock that writes data to its array

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723613 CMOS CLOCKED FIFO WITH

BUS-MATCHING AND BYTE SWAPPING 64 x 36

JANUARY 14, 2009

Number of 36-Bit Synchronized Synchronized

Words in the FIFO

(1)

to CLKB to CLKA

EF AE A F FF

0LLHH

1 to X H L H H

(X + 1) to [64 – (X + 1)] H H H H

(64 – X) to 63 H H L H

64 H H L L

NOTE:

1. X is the value in the Almost-Empty flag and Almost-Full flag Offset register.

TABLE 3 — PORT B ENABLE FUNCTION TABLE

CSB W/RB ENB SIZ1, SIZ0 CLKB B0-B35 Outputs Port Function

H X X X X In high-impedance state None

L H L X X In high-impedance state None

L H H One, both LOW ↑ In high-impedance state None

L H H Both HIGH ↑ In high-impedance state Mail2 write

L L L One, both LOW X Active, FIFO output register None

L L H One, both LOW ↑ Active, FIFO output register FIFO read

L L L Both HIGH X Active, mail1 register None

L L H Both HIGH ↑ Active mail1 register Mail1 read (set MBF1 HIGH)

TABLE 4 — FIFO FLAG OPERATION

(CLKA). When the FF is HIGH, a SRAM location is free to receive new data.

No memory locations are free when the FF is LOW and attempted writes to the

FIFO are ignored.

Each time a word is written to the FIFO, its write-pointer is incremented. The

state machine that controls the FF monitors a write-pointer and read-pointer

comparator that indicates when the FIFO SRAM status is full, full-1, or full-2.

From the time a word is read from the FIFO, its previous memory location is ready

to be written in a minimum of three CLKA cycles. Therefore, a FF is LOW if less

than two CLKA cycles have elapsed since the next memory write location has

been read. The second LOW-to-HIGH transition on the FF synchronizing clock

after the read sets the FF HIGH and data can be written in the following clock

cycle.

A LOW-to-HIGH transition on CLKA begins the first synchronization cycle of

a read if the clock transition occurs at time tSKEW1 or greater after the read.

Otherwise, the subsequent clock cycle can be the first synchronization cycle

(see Figure 11).

ALMOST-EMPTY FLAG (AE)

The FIFO Almost-Empty flag is synchronized to the port clock that reads data

from its array (CLKB). The state machine that controls the AE flag monitors a

write-pointer and read-pointer comparator that indicates when the FIFO SRAM

status is almost-empty, almost-empty+1, or almost-empty+2. The almost-empty

state is defined by the value of the Almost-Full and Almost-Empty Offset register

(X). This register is loaded with one of four preset values during a device reset

(see reset above). The AE flag is LOW when the FIFO contains X or less long

words in memory and is HIGH when the FIFO contains (X+1) or more long

words.

Two LOW-to-HIGH transitions on the port B Clock (CLKB) are required after

a FIFO write for the AE flag to reflect the new level of fill. Therefore, the AE flag

of a FIFO containing (X+1) or more long words remains LOW if two CLKB cycles

have not elapsed since the write that filled the memory to the (X+1) level. The

AE flag is set HIGH by the second CLKB LOW-to-HIGH transition after the FIFO

write that fills memory to the (X+1) level. A LOW-to-HIGH transition of CLKB

begins the first synchronization cycle if it occurs at time t

SKEW2 or greater after

the write that fills the FIFO to (X+1) long words. Otherwise, the subsequent CLKB

cycle can be the first synchronization cycle (see Figure 12).

ALMOST FULL FLAG (AF)

The FIFO Almost-Full flag is synchronized to the port clock that writes data

to its array (CLKA). The state machine that controls an AF flag monitors a write-

pointer and read-pointer comparator that indicates when the FIFO SRAM status

is almost -full, almost- full-1, or almost-full-2. The almost-full state is defined by

the value of the Almost-Full and Almost-Empty Offset register (X). This register

is loaded with one of four preset values during a device reset (see reset above).

The AF flag is LOW when the FIFO contains (64-X) or more long words in

memory and is HIGH when the FIFO contains [64-(X+1)] or less long words.

Two LOW-to-HIGH transitions on the port A Clock (CLKA) are required after

a FIFO read for the AF flag to reflect the new level of fill. Therefore, the AF flag

of a FIFO containing [64-(X+1)] or less words remains LOW if two CLKA cycles

have not elapsed since the read that reduced the number of long words in

memory to [64-(X+1)]. The AF flag is set HIGH by the second CLKA LOW-to-

HIGH transition after the FIFO read that reduces the number of long words in

memory to [64-(X+1)]. A LOW-to-HIGH transition on CLKA begins the first

synchronization cycle if it occurs at time t

SKEW2 or greater after the read that

reduces the number of long words in memory to [64-(X+1)]. Otherwise, the

subsequent CLKA cycle can be the first synchronization cycle (see Figure 13).

MAILBOX REGISTERS

Two 36-bit bypass registers (mail1, mail2) are on the IDT723613 to pass

command and control information between port A and port B without putting it

in queue. A LOW-to-HIGH transition on CLKA writes A0-A35 data to the mail1

HIGH). A LOW-to-HIGH transition on CLKB writes B0-B35 data to the mail2

and SIZ1 are HIGH). Writing data to a mail register sets its corresponding flag

(MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while

its mail flag is LOW.

When the port B data (B0-B35) outputs are active, the data on the bus comes

from the FIFO output register when either one or both SIZ1 and SIZ0 are LOW

and from the mail1 register when both SIZ1 and SIZ0 are HIGH. The Mail1

is selected by CSB, W/RB, and ENB, (and both SIZ1 and SIZ0 HIGH). The

Mail2 Register Flag (MBF2) is set HIGH by a rising CLKA edge when a port

A read is selected by CSA, W/RA, and ENA (with MBA HIGH). The data in a

mail register remains intact after it is read and changes only when new data is

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723613 CMOS CLOCKED FIFO WITH

BUS-MATCHING AND BYTE SWAPPING 64 x 36

JANUARY 14, 2009

TEMPERATURE RANGES

written to the register.

DYNAMIC BUS SIZING

The port B bus can be configured in a 36-bit long word, 18-bit word, or 9-

bit byte format for data read from the FIFO. Word- and byte-size bus selections

can utilize the most significant bytes of the bus (Big-Endian) or least significant

bytes of the bus (Little-Endian). Port B bus-size can be changed dynamically

and synchronous to CLKB to communicate with peripherals of various bus

widths.

The levels applied to the port B bus-size select (SIZ0, SIZ1) inputs and the

Big-Endian select (BE) input are stored on each CLKB LOW-to-HIGH transition.

The stored port B bus-size selection is implemented by the next rising edge on

CLKB according to Figure 2.

Only 36-bit long-word data is written to or read from the FIFO memory on

the IDT723613. Bus-matching operations are done after data is read from the

FIFO RAM. Port B bus sizing does not apply to mail register operations.

BUS-MATCHING FIFO READS

Data is read from the FIFO RAM in 36-bit long-word increments. If a long-

word bus-size is implemented, the entire long word immediately shifts to the FIFO

output register upon a read. If byte or word size is implemented on port B, only

the first one or two bytes appear on the selected portion of the FIFO output

subsequent FIFO reads with the same bus-size implementation output the rest

of the long word to the FIFO output register in the order shown by Figure 2.

Each FIFO read with a new bus-size implementation automatically unloads

data from the FIFO RAM to its output register and auxiliary registers. Therefore,

implementing a new port B bus-size and performing a FIFO read before all bytes

or words stored in the auxiliary registers have been read results in a loss of the

unread data in these registers.

When reading data from FIFO in byte or word format, the unused B0-B35

outputs remain inactive but static, with the unused FIFO output register bits

holding the last data value to decrease power consumption.

BYTE SWAPPING

The byte-order arrangement of data read from the FIFO can be changed

synchronous to the rising edge of CLKB. Byte-order swapping is not available

for mail register data. Four modes of byte-order swapping (including no swap)

can be done with any data port size selection. The order of the bytes are

rearranged within the long word, but the bit order within the bytes remains

constant.

Byte arrangement is chosen by the port B Swap select (SW0, SW1) inputs

on a CLKB rising edge that reads a new long word from the FIFO. The byte

order chosen on the first byte or first word of a new long word read from the FIFO

is maintained until the entire long word is transferred, regardless of the SW0 and

SW1 states during subsequent reads. Figure 4 is an example of the byte-order

swapping available for long word reads. Performing a byte swap and bus-size

simultaneously for a FIFO read first rearranges the bytes as shown in Figure

4, then outputs the bytes as shown in Figure 2.

PORT-B MAIL REGISTER ACCESS

In addition to selecting port B bus sizes for FIFO reads, the port B bus Size

select (SIZ0, SIZ1) inputs also access the mail registers. When both SIZ0 and

SIZ1 are HIGH, the mail1 register is accessed for a port B long-word read and

the mail2 register is accessed for a port B long-word write. The mail register is

accessed immediately and any bus-sizing operation that can be underway is

unaffected by the mail register access. After the mail register access is complete,

the previous FIFO access can resume in the next CLKB cycle. The logic diagram

in Figure 3 shows the previous bus-size selection is preserved when the mail

registers are accessed from port B. A port B bus-size is implemented on each

rising CLKB edge according to the states of SIZ0_Q, SIZ1_Q, and BE_Q.

PARITY CHECKING

The port A data inputs (A0-A35) and port B data inputs (B0-B35) each have

four parity trees to check the parity of incoming (or outgoing) data. A parity failure

on one or more bytes of the port A data bus is reported by a low level on the

port A Parity Error Flag (PEFA). A parity failure on one or more bytes of the

port B data inputs that are valid for the bus-size implementation is reported by

a low level on the port B Parity Error Flag (PEFB). Odd or Even parity checking

can be selected, and the Parity Error Flags can be ignored if this feature is not

desired.

Parity status is checked on each input bus according to the level of the Odd/

Even parity (ODD/EVEN) select input. A parity error on one or more valid bytes

of a port is reported by a LOW level on the corresponding port Parity Error Flag

(PEFA, PEFB) output. Port A bytes are arranged as A0-A8, A9-A17, A18-A26,

and A27-A35, and port B bytes are arranged as B0-B8, B9-B17, B18-B26, and

B27-B35, and its valid bytes are those used in a port B bus size implementation.

When Odd/Even parity is selected, a port Parity Error Flag (PEFA, PEFB) is

LOW if any byte on the port has an odd/even number of LOW levels applied

to its bits.

The four parity trees used to check the A0-A35 inputs are shared by the mail2

When a port A read from the mail2 register with parity generation is selected with

CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA HIGH, the port A

Parity Error Flag (PEFA) is held HIGH regardless of the levels applied to the

A0-A35 inputs. Likewise, the parity trees used to check the B0-B35 inputs are

shared by the mail1 register when parity generation is selected for port B reads

(PGB = HIGH). When a port B read from the mail1 register with parity generation

is selected with CSB LOW, ENB HIGH, W/RB LOW, both SIZ0 and SIZ1 HIGH,

and PGB HIGH, the port B Parity Error Flag (PEFB) is held HIGH regardless

of the levels applied to the B0-B35 inputs.

PARITY GENERATION

A HIGH level on the port A Parity Generate select (PGA) or port B Parity

Generate select (PGB) enables the IDT723613 to generate parity bits for port

reads from a FIFO or mailbox register. Port A bytes are arranged as A0-A8,

A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte used

as the parity bit. Port B bytes are arranged as B0-B8, B9-B17, B18-B26, and

B27-B35, with the most significant bit of each byte used as the parity bit. A write

to a FIFO or mail register stores the levels applied to all nine inputs of a byte

regardless of the state of the Parity Generate select (PGA, PGB) inputs. When

data is read from a port with parity generation selected, the lower eight bits of

each byte are used to generate a parity bit according to the level on the ODD/

EVEN select. The generated parity bits are substituted for the levels originally

written to the most significant bits of each byte as the word is read to the data

outputs.

Parity bits for FIFO data are generated after the data is read from SRAM

and before the data is written to the output register. Therefore, the port A Parity

Generate select (PGA) and Odd/Even parity select (ODD/EVEN) have setup

and hold time constraints to the port A Clock (CLKA) and the port B Parity

Generate select (PGB) and ODD/EVEN select have setup and hold time

constraints to the port B Clock (CLKB). These timing constraints only apply

for a rising clock edge used to read a new long word to the FIFO output register.

The circuit used to generate parity for the mail1 data is shared by the port B

bus (B0-B35) to check parity and the circuit used to generate parity for the mail2

data is shared by the port A bus (A0-A35) to check parity. The shared parity

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P26

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