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CY26049ZXC-22T

P1-P3P4-P6
CY26049-22
FailSafe™ PacketClock™
Global Communications Clock Generato
r
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07730 Rev. ** Revised January 12, 2005
Features
• Fully integrated phase-locked loop (PLL)
• FailSafe output
• PLL driven by a crystal oscillator that is phase aligned
with external reference
• 100-MHz output from 10-MHz input
• Low-jitter, high-accuracy outputs
• 3.3V ± 5% operation
• 16-lead TSSOP
Benefits
• Integrated high-performance PLL tailored for telecommuni-
cations frequency synthesis eliminates the need for external
loop filter components
• When reference is off, DCXO maintains clock outputs and
SAFE pin indicates FailSafe conditions
• DCXO maintains continuous operation should the input
reference clock fail
• Glitch-free transition simplifies system design
• Works with commonly available, low-cost 10-MHz crystal
• Zero-ppm error for all output frequencies
• Compatible across industry standard design platforms
• Industry standard package with 6.4 × 5.0 mm
2
footprint and
a height profile of just 1.1 mm
X
IN
XOUT
ICLK
CLKA
100MHz
SAFE
input reference
(10MHz)
external pullable crystal
(10MHz)
DIGITAL
CONTROLLED
CRYSTAL
OSCILLATOR
FAILSAFE
TM
CONTROL
PHASE
LOCKED
LOOP
OUTPUT
DIVIDER
ICLK detected
Logic Block Diagram
CY26049-22
Document #: 38-07730 Rev. ** Page 2 of 6
Pin Configuration
Description
CY26049-22 is a FailSafe frequency synthesizer with a
reference clock input and 100-MHz output. The device
provides an optimum solution for applications where
continuous operation is required in the event of a primary clock
failure. The continuous, glitch-free operation is achieved by
using a DCXO, which serves as a primary clock source. The
FailSafe control circuit synchronizes the DCXO oscillator with
the reference as long as the reference is within the pull range
of the crystal.
In the event of a reference clock failure the DCXO maintains
the last frequency of the reference clock. The unique feature
of the CY26049-22 is that the DCXO is, in fact, the primary
clocking source. When the reference clock is restored, the
DCXO automatically resynchronizes to the reference. The
status of the reference clock input, as detected by the
CY26049-22, is reported by the SAFE pin.
Pin Description
Pin Number Pin Name Pin Description
1ICLKReference Input Clock; 10 MHz.
2NC No Connect.
3NCNo Connect.
4NCNo Connect.
5VDDVoltage Supply; 3.3V.
6VSSGround.
7NCNo Connect
8XINPullable Crystal Input; 10 MHz.
9XOUTPullable Crystal Output; 10 MHz.
10 SAFE High = reference ICLK within range, Low = reference ICLK out of range.
11 VSS Ground.
12 VDD Voltage Supply; 3.3V.
13 NC No Connect.
14 NC No Connect.
15 CLKA Clock Output. 100 MHz
16 NC No Connect.
Selector Guide
Part Number Input Frequency Range Outputs Output Frequencies
CY26049ZXC-22 Reference Input Clock: 10 MHz
Crystal: 10-MHz pullable Crystal per Cypress Specification
1 100 MHz
ICLK 1 16 NC
NC 2 15
CLKA
NC
3 14 NC
NC 4 13 NC
VDD 5 12 VDD
VSS 6 11 VSS
NC 7 10 SAFE
XIN 8 9 XOUT
16-pin TSSOP
Top View
CY26049-22
Document #: 38-07730 Rev. ** Page 3 of 6
Absolute Maximum Conditions
Supply Voltage (V
DD
) ........................................–0.5 to +7.0V
DC Input Voltage...................................... –0.5V to V
DD
+ 0.5
Storage Temperature (Non-Condensing) ....–55°C to +125°C
Junction Temperature ................................ –40°C to +125°C
Data Retention @ Tj = 125°C................................ >10 Years
Package Power Dissipation...................................... 350 mW
ESD (Human Body Model) MIL-STD-883.................... 2000V
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Recommended Pullable Crystal Specifications
Parameter Name Comments Min. Typ. Max. Unit
F
NOM
Nominal crystal frequency Parallel resonance, fundamental mode,
AT cut
–10–MHz
C
LNOM
Nominal load capacitance – 14 – pF
R
1
Equivalent series resistance (ESR) Fundamental mode – – 25 Ω
R
3
/R
1
Ratio of third overtone mode ESR to
fundamental mode ESR
Ratio used because typical R
1
values
are much less than the maximum spec
3––
DL Crystal drive level No external series resistor assumed – 0.5 2 mW
F
3SEPLI
Third overtone separation from 3*F
NOM
High side 400 – – ppm
F
3SEPLO
Third overtone separation from 3*F
NOM
Low side – – –200 ppm
C
0
Crystal shunt capacitance – – 7 pF
C
0
/C
1
Ratio of shunt to motional capacitance 180 – 250
C
1
Crystal motional capacitance 14.4 18 21.6 fF
Recommended Operating Conditions
Parameter Description Min. Typ. Max. Unit
V
DD
Operating Voltage 3.15 3.3 3.45 V
T
AC
Ambient Temperature (Commercial Temperature) 0 – 70 °C
C
LOAD
Max Output Load Capacitance – – 15 pF
t
pu
Power-up time for all V
DD
s to reach minimum specified
voltage (power ramps must be monotonic)
0.05 – 500 ms
DC Electrical Specifications (Commercial Temp: 0°to 70°C)
Parameter Description Test Conditions Min. Typ. Max. Unit
I
OH
Output High Current V
OH
= V
DD
– 0.5, V
DD
= 3.3V (source) 12 24 – mA
I
OL
Output Low Current V
OL
= 0.5, V
DD
= 3.3V (sink) 12 24 – mA
V
IH
Input High Voltage CMOS Levels 0.7 – – V
DD
V
IL
Input High Voltage CMOS Levels – – 0.3 V
DD
I
IH
Input High Current V
IH
=V
DD
–510µA
I
IL
Input Low Current V
IL
=0V – 5 10 µA
C
IN
Input Capacitance – – 7 pF
I
DD
Supply Current C
LOAD
= 15 pF, V
DD
= 3.45V – – 45 mA
AC Electrical Specifications (Commercial Temp: 0° to 70°C)
Parameter Description Test Conditions Min. Typ. Max. Unit
f
ICLK-E
Frequency, Input Clock Input Clock Frequency, External Mode – 10 – MHz
LR FailSafe
Lock Range
[1]
Range of reference ICLK for Safe = High –250 – +250 ppm
DC = t
2
/t
1
Output Duty Cycle Duty Cycle defined in Figure 1, measured at 50% of V
DD
45 50 55 %
T
PJIT1
Clock Jitter Period Jitter, Peak to Peak, 10,000 periods – – 250 ps
RMS Period Jitter – – 50 ps
Note:
1. Dependent on crystals chosen and crystal specs.
P1-P3P4-P6

CY26049ZXC-22T

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Manufacturer:
Cypress Semiconductor
Description:
Phase Locked Loops - PLL FailSafe Clock COM
Lifecycle:
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