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CY26049ZXC-22T

P1-P3P4-P6
CY26049-22
Document #: 38-07730 Rev. ** Page 4 of 6
Voltage and Timing Definitions
Test Circuit
t
6
PLL Lock Time Time for PLL to lock within ± 150 ppm of target frequency – – 3 ms
t
fs_lock
FailSafe Lock Time Time for PLL to lock to ICLK (outputs phase aligned with
ICLK and Safe = High)
––7s
f
error
Frequency Synthesis Error Actual mean frequency error vs. target – 0 – ppm
ER Rising Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of
V
DD
, C
LOAD
= 15 pF. See Figure 2.
0.8 1.4 2 V/ns
EF Falling Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of
V
DD
, C
LOAD
= 15 pF. See Figure 2.
0.8 1.4 2 V/ns
AC Electrical Specifications (Commercial Temp: 0° to 70°C) (continued)
Parameter Description Test Conditions Min. Typ. Max. Unit
t1
t2
50%
50%
CLK
Figure 1. Duty Cycle Definition; DC = t2/t1
Figure 2. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3, EF = 0.6 x VDD / t4
CLK
t3
t4
80%
20%
Ordering Information
Ordering Code Package Type Operating Temperature Range
Lead-Free
CY26049ZXC-22 16-lead TSSOP Commercial 0° to 70°C
CY26049ZXC-22T 16-lead TSSOP—Tape and Reel Commercial 0° to 70°C
0.1uF
V
DD
ICLK
0.1uF
V
DD
16
4
3
2
1
9
10
11
12
13
15
14
5
6
7
8
10MHz
CLK
A
C
LOAD
CY26049-22
Document #: 38-07730 Rev. ** Page 5 of 6
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Package Drawing and Dimensions
FailSafe and PacketClock are trademarks of Cypress Semiconductor. Corporation. All product and company names mentioned
in this document are the trademarks of their respective holders.
4.90[0.193]
1.10[0.043] MAX.
0.65[0.025]
0.20[0.008]
0.05[0.002]
16
PIN1ID
6.50[0.256]
SEATING
PLANE
1
0.076[0.003]
6.25[0.246]
4.50[0.177]
4.30[0.169]
BSC.
5.10[0.200]
0.15[0.006]
0.19[0.007]
0.30[0.012]
0.09[[0.003]
BSC
0.25[0.010]
0°-8°
0.70[0.027]
0.50[0.020]
0.95[0.037]
0.85[0.033]
PLANE
GAUGE
DIMENSIONS IN MM[INCHES] MIN.
MAX.
REFERENCE JEDEC MO-153
PACKAGE WEIGHT 0.05gms
16-lead TSSOP 4.40 MM Body Z16.173
51-85091-*A
CY26049-22
Document #: 38-07730 Rev. ** Page 6 of 6
Document History Page
Document Title: CY26049-22 FailSafe™ PacketClock™ Global Communications Clock Generator
Document Number: 38-07730
REV. ECN No. Issue Date
Orig. of
Change Description of Change
** 308456 See ECN RGL New Data Sheet
P1-P3P4-P6

CY26049ZXC-22T

Mfr. #:
Buy CY26049ZXC-22T
Manufacturer:
Cypress Semiconductor
Description:
Phase Locked Loops - PLL FailSafe Clock COM
Lifecycle:
New from this manufacturer.
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