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LTC4312IMS#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
LTC4312
10
4312f
APPLICATIONS INFORMATION
Figure 3. Connection of the LTC4312 in a Level Shift Application. V
CC2
Is
Less Than or Equal to the Minimum Bus Supply Voltage on the Output Side
If V
CC2
is tied low, the output side rise time accelerators
are disabled independent of the state of the ACC pin.
ACC tied high disables input and output RTAs. Using a
combination of the ACC pin and the V
CC2
voltage allows
the user independent control of the input and output side
rise time accelerators. The rise time accelerators are also
internally disabled during power-up and V
CC2
transitions,
as described in the Operation section, as well as during
automatic clocking and stop bit generation for a bus stuck
low recovery event.
The rise time accelerators when activated pull the bus up
to 0.9•V
CC
on the input side of the SDA and SCL lines.
On the output side the SDAOUT and SCLOUT lines are
pulled up by the rise time accelerators to 0.8•V
CC2
. For
V
CC2
voltages approaching 2.3V, acceleration of the output
bus may not be seen all the way to 0.8•V
CC2
due to the
threshold voltage of the NFET pass device.
Supply Voltage Considerations in Level Translation
Applications
Care must be taken to ensure that the bus supply voltages
on the input and output sides are greater than 0.9•V
CC
and
0.8•V
CC2
, respectively, to ensure that the bus is not driven
above the bus supplies by the rise time accelerators. This
is usually accomplished in a level shifting application by
tying V
CC
to the input bus supply and V
CC2
to the minimum
bus supply on the output side as shown in Figure 3.
If V
CC2
is grounded, the multiplexer pass gates are powered
from V
CC
. In this case the minimum output bus supply
of the enabled channels should be greater than or equal
to V
CC
to prevent cross-conduction between the enabled
output channels. This is shown in Figure 4. Grounding V
CC2
as shown in Figure 4 disables the output side rise time
accelerators independent of the state of the ACC pin. The
input rise time accelerators in this confi guration continue
to be controlled by the ACC pin and can be enabled inde-
pendently. In Figure 4, ACC is left open to obtain a high V
IL
and a 3mA rise time accelerator current on the input side.
LTC4312
GND
V
CC
V
CC2
4312 F03
SCLOUT1
SDAOUT1
SCLOUT2
SDAOUT2
SCLOUT1
SDAOUT1
SCLOUT2
SDAOUT2
SCLIN
SDAIN
ENABLE1
ENABLE2
ACC
DISCEN
FAULT
SCLIN
SDAIN
ENABLE1
ENABLE2
3.3V
FAULT
R3
10k
R2
10k
R1
10k
C1
0.01μF
3.3V 3.3V
R5
10k
R4
10k
C2
0.01μF
5V
R7
10k
R6
10k
LTC4312
11
4312f
APPLICATIONS INFORMATION
Pull-Up Resistor Value Selection
To guarantee that the rise time accelerators are activated
during a rising edge, the bus must rise on its own with
a positive slew rate of at least 0.4V/μs. To achieve this,
choose a maximum R
BUS
using equation 1:
R
BUS
(Ω)≤
V
DD,BUS(MIN)
− V
RTA(TH)
()
0.4
V
µs
•C
BUS
(1)
R
BUS
is the bus pull-up resistor, V
DD, BUS(MIN)
the minimum
bus pull-up supply voltage, V
RTA(TH)
the voltage at which
the rise time accelerator turns on, which is a function of
ACC, and C
BUS
the equivalent bus capacitance. R
BUS
values
on each output channel must also be chosen to ensure
that when all the required output channels are enabled, the
total bus current is ≤4mA. The bus current in each output
channel can be 4mA if only one output channel is enabled
at any given time. The R
BUS
value on the input side must
also be chosen to limit the bus current to be ≤4mA. The
bus current for a single bus is determined by equation 2:
I
BUS
(A)=
V
DD,BUS
− 0.4V
R
BUS
(2)
Input to Output Offset Voltage and Propagation Delay
The LTC4312 introduces both an offset as well as a
propagation delay for falling edges between the input and
output. When a logic low voltage of ≥200mV is driven
on any of the LTC4312’s data or clock pins, the LTC4312
regulates the voltage on the opposite side to a slightly
higher value. When SCLIN or SDAIN is driven to a logic
low voltage, SCLOUT or SDAOUT is driven to a slightly
higher voltage as directed by equation 3 which uses SDA
as an example:
V
SDAOUT
(V)= V
SDAIN
+ 45mV
+ (10Ω + R
MUX
)•
V
DD,BUS
R
BUS
(3)
V
DD,BUS
is the output bus voltage, R
BUS
the output bus
pull-up resistance and R
MUX
is the resistance of the channel
transmission gate in the multiplexer shown in the block
diagram. The offset is affected by the V
CC2
voltage and bus
current. A higher V
CC2
voltage (V
CC
if V
CC2
is grounded)
reduces R
MUX
leading to a lower offset. See the Typical
Performance Characteristics plots for the variation of R
MUX
as a function of V
CC2
and temperature. When SDAOUT or
SCLOUT is driven to a logic low voltage ≥ 200mV, SCLIN
Figure 4. Connection of the LTC4312 in a Level Shift Application. V
CC
Is Less Than or Equal to the Minimum
Bus Supply Voltages on the Output Side. V
CC2
Is Grounded to Disable Output Rise Time Accelerators
LTC4312
GND
V
CC
V
CC2
4312 F04
SCLOUT1
SDAOUT1
SCLOUT2
SDAOUT2
SCLOUT1
SDAOUT1
SCLOUT2
SDAOUT2
SCLIN
SDAIN
ENABLE1
ENABLE2
ACC
DISCEN
FAULT
SCLIN
SDAIN
ENABLE1
ENABLE2
3.3V
FAULT
R3
10k
R2
10k
R1
10k
C1
0.01μF
C2
0.01μF
3.3V 3.3V
R5
10k
R4
10k
5V
R7
10k
R6
10k
LTC4312
12
4312f
Figure 5. Cascading LTC4312s with Other LTC4312s and LTC Bus Buffers. Only the SDA Path Is Shown for Simplicity
or SDAIN is regulated to a logic low voltage as directed
by equation 4 which uses SDA as an example:
V
SDAIN
(V)= V
SDAOUT
+ 45mV +10Ω •
V
DD,BUS
R
BUS
(4)
The SCLOUT/SDAOUT to SCLIN/SDAIN offset is lower
than the reverse case as the multiplexer transmission gate
does not affect this offset. For driven logic low voltages
< 200mV, the above equations do not apply as the saturation
voltage of the open collector output transistor results in a
higher offset. However, the offset is guaranteed to be less
than 400mV for a total bus pull-up current of 4mA under
all conditions. See the Typical Performance Characteristics
curves for the buffer offset voltage as a function of the
driven logic low voltage and bus pull-up current.
The high-to-low propagation delay arises due to both the
fi nite response time of the buffers and their fi nite current
sink capability. See the Typical Performance Characteristics
curves for the propagation delay as a function of the bus
capacitance.
APPLICATIONS INFORMATION
Cascading LTC4312 Devices and Other LTC Bus Buffers
Multiple LTC4312s can be cascaded or the LTC4312 may
be cascaded with other LTC bus buffers as required by the
application. This is shown for the data pathway in Figure 5
where an LTC4312 is cascaded with other LTC4312s and
some select LTC bus buffers. The clock path is identical.
When using such cascades, users should be aware of the
additive logic low offset voltages (V
OS
) when determin-
ing system noise margin. If the sum of the offsets (refer
to Equations 3 and 4 and to the data sheets of the cor-
responding bus buffers) plus the worst-case driven logic
low voltage across the cascade exceeds the buffer turn off
voltage, signals will not be propagated across the cascade.
Also the minimum rise time accelerator (RTA) turn-on volt-
age (wherever applicable) of each device in the cascade
should also be greater than the maximum buffer turn-off
voltage of all the devices in the cascade. This condition
is required to prevent contention between one device’s
buffer and another’s RTA. Based on this requirement,
LTC4312
GND
3.3V
R1
10k
C1
0.01μF
V
CC
V
CC2
4312 F05
SDAOUT1
SDAOUT2
SDAIN
ACC
3.3V
LTC4312
V
CC
V
CC2
SDAOUT1
SDAOUT2
SDAIN
ACC
LTC4301
GND
V
CC
SDAOUTSDAIN
5V
LTC4312
GND
3.3V
C2
0.01μF
V
CC
V
CC2
SDAOUT1
SDAOUT2
SDAIN
ACC
C3
0.01μF
R2
10k
R3
10k
R4
10k
C4
0.01μF
C5
0.01μF
R5
10k
R6
10k
5V
3.3V
R7
10k
SDAOUT1
SDAOUT2
SDAOUT3
SDAOUT4
SDAOUT5
LTC4303
V
CC
SDAOUTSDAIN
5V
R8
10k
LTC4307
V
CC
SDAOUTSDAIN
5V
R9
10k
GND
GND
GND
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

LTC4312IMS#TRPBF

Mfr. #:
Buy LTC4312IMS#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Multiplexer Switch ICs Pin-Sel, 2-Ch, 2-Wire Multxer w/ Bus Buf
Lifecycle:
New from this manufacturer.
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