HMC674LC3C/HMC674LP3E Data Sheet
Rev. K | Page 10 of 14
THEORY OF OPERATION
The HMC674LC3C/HMC674LP3E are latched comparators
with a 9.3 GHz equivalent input bandwidth. These devices are
comprised of three blocks: an input amplifier, a latch, and an
output buffer. The latching circuit is level sensitive and consists
of a single, high speed latch. The HMC674LC3C/HMC674LP3E
comparators support 10 Gbps operation. The input signal
minimum pulse width is 60 ps.
The HMC674LC3C/HMC674LP3E operate in either track
(transparent) mode, where the output follows the logical value
of the input, or latch (hold) mode, where the output value is held
to the logical value of the comparison result of the input just
prior to (LE −
LE
) going high. Select track mode operation by
either setting (LE −
LE
) low or by floating the LE and
LE
inputs.
Select latch mode by setting (LE −
LE
) high. The input impedance
of the LE and
LE
inputs is 8 kΩ; however, these inputs can be
terminated with 50 Ω external resistors, if desired.
When the clock inputs are dc-coupled, they operate at an input
common-mode voltage of 2 V. In this case, any termination
resistors ideally return to 2 V. If the clock inputs are ac-coupled
to the HMC674LC3C/HMC674LP3E, return the input
termination resistors to ground.
POWER SEQUENCING
As long as the input signal is not near the −2 V extreme, either
V
CC
or V
EE
can be powered on first. However, if the input voltage is
more negative than −1.8 V, use the following power-up sequence:
1. V
EE
2. V
CCI
and V
CCO
(if V
CCO
= V
CCI
)
3. V
CCO
(if different than ground)
Note that the power-down sequence is the reverse of this
sequence.
It is recommended to power up the HMC674LC3C or the
HMC674LP3E before applying the input signal and to remove the
input signal prior to powering either down. These recommendations
are important if any of the inputs are more negative than −1.8 V.
