Data Sheet
ADP3654
Rev. A | Page 9 of 13
THEORY OF OPERATION
The ADP3654 dual driver is optimized for driving two
independent enhancement N-channel MOSFETs or insulated
gate bipolar transistors (IGBTs) in high switching frequency
applications.
These applications require high speed, fast rise and fall times, as
well as short propagation delays. The capacitive nature of the
aforementioned gated devices requires high peak current
capability as well.
INA
VDD
V
DD
PGND
ADP3654
OUTA
OUTBINB
NC
NC
1
3
8
7
6
5
A
B
2
4
V
DS
V
DS
09054-015
Figure 15. Typical Application Circuit
INPUT DRIVE REQUIREMENTS (INA AND INB)
The ADP3654 is designed to meet the requirements of modern
digital power controllers; the signals are compatible with 3.3 V
logic levels. At the same time, the input structure allows for
input voltages as high as V
DD
.
An internal pull-down resistor is present at the input, which
guarantees that the power device is off in the event that the
input is left floating.
LOW-SIDE DRIVERS (OUTA, OUTB)
The ADP3654 dual drivers are designed to drive ground
referenced N-channel MOSFETs. The bias is internally
connected to the V
DD
supply and PGND.
When ADP3654 is disabled, both low-side gates are held low.
Internal impedance is present between the OUTA pin and GND
and between the OUTB pin and GND; this feature ensures that
the power MOSFET is normally off when bias voltage is not
present.
When interfacing ADP3654 to external MOSFETs, the designer
should consider ways to make a robust design that minimizes
stresses on both the driver and the MOSFETs. These stresses
include exceeding the short time duration voltage ratings on the
OUTA and OUTB pins, as well as the external MOSFET.
Power MOSFETs are usually selected to have a low on resistance
to minimize conduction losses, which usually implies a large
input gate capacitance and gate charge.
SUPPLY CAPACITOR SELECTION
For the supply input (V
DD
) of the ADP3654, a local bypass
capacitor is recommended to reduce the noise and to supply
some of the peak currents that are drawn.
An improper decoupling can dramatically increase the rise
times because excessive resonance on the OUTA and OUTB
pins can, in some extreme cases, damage the device, due to
inductive overvoltage on the VDD, OUTA, or OUTB pin.
The minimum capacitance required is determined by the size
of the gate capacitances being driven, but as a general rule, a
4.7 µF, low ESR capacitor should be used. Multilayer ceramic
chip (MLCC) capacitors provide the best combination of low
ESR and small size. Use a smaller ceramic capacitor (100 nF)
with a better high frequency characteristic in parallel to the
main capacitor to further reduce noise.
Keep the ceramic capacitor as close as possible to the ADP3654
device and minimize the length of the traces going from the
capacitor to the power pins of the device.
PCB LAYOUT CONSIDERATIONS
Use the following general guidelines when designing PCBs:
• Trace out the high current paths and use short, wide
(>40 mil) traces to make these connections.
• Minimize trace inductance between the OUTA and OUTB
outputs and MOSFET gates.
• Connect the PGND pin of the ADP3654 device as closely
as possible to the source of the MOSFETs.
• Place the V
DD
bypass capacitor as close as possible to the
VDD and PGND pins.
• Use vias to other layers, when possible, to maximize
thermal conduction away from the IC.
