Data Sheet
ADP3654
Rev. A | Page 3 of 13
SPECIFICATIONS
V
DD
= 12 V, T
J
= −40°C to +125°C, unless otherwise noted.
1
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SUPPLY
Supply Voltage Range V
DD
4.5 18 V
Supply Current I
DD
No switching 1.2 3 mA
UVLO
Turn-On Threshold Voltage V
UVLO_ON
V
DD
rising, T
J
= 25°C, see Figure 3 3.8 4.2 4.5 V
Turn-Off Threshold Voltage V
UVLO_OFF
V
DD
falling, T
J
= 25°C, see Figure 3 3.5 3.9 4.3 V
Hysteresis 0.3 V
DIGITAL INPUTS (INA, INB)
Input Voltage High V
IH
See Figure 2 2.0 V
Input Voltage Low V
IL
See Figure 2 0.8 V
Input Current I
IN
0 V < V
IN
< V
DD
−20 +20 µA
Internal Pull-Up/Pull-Down Current 6 µA
OUTPUTS (OUTA, OUTB)
Output Resistance, Unbiased VDD = PGND 80 kΩ
Peak Source Current See Figure 14 4 A
Peak Sink Current See Figure 14 −4 A
SWITCHING TIME
OUTA and OUTB Rise Time t
RISE
C
LOAD
= 2.2 nF, see Figure 2 10 25 ns
OUTA and OUTB Fall Time t
FALL
C
LOAD
= 2.2 nF, see Figure 2 10 25 ns
OUTA and OUTB Rising Propagation Delay t
D1
C
LOAD
= 2.2 nF, see Figure 2 14 30 ns
OUTA and OUTB Falling Propagation Delay t
D2
C
LOAD
= 2.2 nF, see Figure 2 22 35 ns
Delay Matching Between Channels 2 ns
1
All limits at temperature extremes guaranteed via correlation using standard statistical quality control (SQC) methods.
TIMING DIAGRAMS
INA,
INB
OUTA,
OUTB
t
D1
t
RISE
10%
90%
10%
90%
V
IH
V
IL
t
D2
t
FALL
09054-002
Figure 2. Output Timing Diagram
NORMAL OPERATIONUVLO MODE
OUTPUTS DISABLED
V
DD
V
UVLO_ON
V
UVLO_OFF
UVLO MODE
OUTPUTS DISABLED
09054-003
Figure 3. UVLO Function
ADP3654
Data Sheet
Rev. A | Page 4 of 13
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VDD −0.3 V to +20 V
OUTA, OUTB
DC −0.3 V to V
DD
+ 0.3 V
<200 ns −2 V to V
DD
+ 0.3 V
INA, INB −0.3 V to V
DD
+ 0.3 V
ESD
Human Body Model (HBM) 3.5 kV
Field Induced Charged Device Model
(FICDM)
SOIC_N_EP 1.5 kV
MINI_SO_EP 1.0 kV
θ
JA
, JEDEC 4-Layer Board
SOIC_N_EP
1
59°C/W
MINI_SO_EP
1
43°C/W
Junction Temperature Range −40°C to +150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature
Soldering (10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 260°C
1
θ
JA
is measured per JEDEC standards, JESD51-2, JESD51-5, and JESD51-7, as
appropriate with the exposed pad soldered to the PCB.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Data Sheet
ADP3654
Rev. A | Page 5 of 13
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC
1
INA
2
PGND
3
INB
4
NC
8
OUTA
7
VDD
6
OUTB
5
ADP3654
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT.
2.
THE EXPOSED PAD OF THE PACKAGE IS NOT DIRECTLY
CONNECTED TO ANY PIN OF THE PACKAGE, BUT IT IS
ELECTRICALLY AND THERMALLY CONNECTED TO THE DIE
SUBSTRATE, WHICH IS THE GROUND OF THE DEVICE. IT IS
RECOMMENDED TO HAVE THE EXPOSED PAD AND THE
PGND PIN CONNECTED ON THE PCB.
09054-004
Figure 4. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 NC No Connect.
2 INA Input Pin for Channel A Gate Driver.
3 PGND Ground. This pin should be closely connected to the source of the power MOSFET.
4 INB Input Pin for Channel B Gate Driver.
5
OUTB
Output Pin for Channel B Gate Driver.
6 VDD Power Supply Voltage. Bypass this pin to PGND with a ~1 µF to 5 µF ceramic capacitor.
7 OUTA Output Pin for Channel A Gate Driver.
8 NC No Connect.
9 EPAD Exposed Pad. The exposed pad of the package is not directly connected to any pin of the package, but it is
electrically and thermally connected to the die substrate, which is the ground of the device. It is recommended
to have the exposed pad and the PGND pin connected on the PCB.

ADP3654ARHZ-RL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Gate Drivers High Speed Dual 4A MOSFET Dvr
Lifecycle:
New from this manufacturer.
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