DATA SHEET
ICS853S0121AKI REVISION A SEPTEMBER 28, 2012 1 ©2012 Integrated Device Technology, Inc.
12:1, Differential-to-3.3V, 2.5V
LVPECL Clock/Data Multiplexer
ICS853S012I
General Description
The ICS853S012I is an 12:1 Differential-to-3.3V or 2.5V LVPECL
Clock/Data Multiplexer which can operate up to 3.2GHz. The
ICS853S012I has twelve differential selectable clock inputs. The
CLK, nCLK input pairs can accept LVPECL, LVDS or CML levels.
The fully differential architecture and low propagation delay make it
ideal for use in clock distribution circuits. The select pins have
internal pulldown resistors.
Features
High speed 12:1 differential multiplexer
One differential 3.3V or 2.5V LVPECL output
Twelve selectable differential clock or data inputs
CLKx, nCLKx pairs can accept the following differential input
levels: LVPECL, LVDS, CML
Maximum output frequency: 3.2GHz
Translates any single ended input signal to LVPECL levels with
resistor bias on nCLKx input
Additive phase jitter, RMS: 0.144ps (typical)
Part-to-part skew: 250ps (maximum)
Propagation delay: 1.15ns (maximum)
Full 3.3V or 2.5V operating supply modes
-40°C to 85°C ambient operating temperature
Available lead-free (RoHS 6) package
CLK0
nCLK0
CLK1
nCLK1
CLK2
nCLK2
Q
n
Q
CLK11
nCLK11
SEL[3:0]
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pulldown
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
CLK2
nCLK2
V
CC
Q
nQ
V
EE
CLK3
nCLK3
CLK9
nCLK9
SEL0
SEL1
SEL2
SEL3
CLK8
nCLK8
nCLK4
CLK4
nCLK5
CLK5
CLK6
nCLK6
CLK7
nCLK7
CLK1
nCLK0
CLK0
CLK11
nCLK11
CLK10
nCLK10
nCLK1
ICS853S012I
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
Pin Assignment
Block Diagram
ICS853S012I Data Sheet 12-:1, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL CLOCK/DATA MULTIPLEXER
ICS853S0121AKI REVISION A SEPTEMBER 28, 2012 2 ©2012 Integrated Device Technology, Inc.
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Number Name Type Description
1 CLK2 Input Pulldown Non-inverting differential clock input.
2 nCLK2 Input
Pullup/
Pulldown
Inverting differential clock input. V
CC
/2 default when left floating.
3V
CC
Power Positive supply pin.
4, 5
Q, nQ
Output Differential output pair. LVPECL interface levels.
6V
EE
Power Negative supply pin.
7 CLK3 Input Pulldown Non-inverting differential clock input.
8 nCLK3 Input
Pullup/
Pulldown
Inverting differential clock input. V
CC
/2 default when left floating.
9 nCLK4 Input
Pullup/
Pulldown
Inverting differential clock input. V
CC
/2 default when left floating.
10 CLK4 Input Pulldown Inverting differential clock input.
11 nCLK5 Input
Pullup/
Pulldown
Inverting differential clock input. V
CC
/2 default when left floating.
12 CLK5 Input Pulldown Inverting differential clock input.
13 CLK6 Input Pulldown Non-inverting differential clock input.
14 nCLK6 Input
Pullup/
Pulldown
Inverting differential clock input. V
CC
/2 default when left floating.
15 CLK7 Input Pulldown Non-inverting differential clock input.
16 nCLK7 Input
Pullup/
Pulldown
Inverting differential clock input. V
CC
/2 default when left floating.
17 nCLK8 Input
Pullup/
Pulldown
Inverting differential clock input. V
CC
/2 default when left floating.
18 CLK8 Input Pulldown Inverting differential clock input.
19, 20,
21, 22
SEL3, SEL2,
SEL1, SEL0
Input Pulldown Clock select input pins. LVCMOS/LVTTL interface levels.
23 nCLK9 Input
Pullup/
Pulldown
Inverting differential clock input. V
CC
/2 default when left floating.
24 CLK9 Input Pulldown Inverting differential clock input.
25 nCLK10 Input
Pullup/
Pulldown
Inverting differential clock input. V
CC
/2 default when left floating.
26 CLK10 Input Pulldown Inverting differential clock input.
27 nCLK11 Input
Pullup/
Pulldown
Inverting differential clock input. V
CC
/2 default when left floating.
28 CLK11 Input Pulldown Inverting differential clock input.
29 CLK0 Input Pulldown Inverting differential clock input.
30 nCLK0 Input
Pullup/
Pulldown
Inverting differential clock input. V
CC
/2 default when left floating.
31 CLK1 Input Pulldown Inverting differential clock input.
32 nCLK1 Input
Pullup/
Pulldown
Inverting differential clock input. V
CC
/2 default when left floating.
ICS853S012I Data Sheet 12-:1, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL CLOCK/DATA MULTIPLEXER
ICS853S0121AKI REVISION A SEPTEMBER 28, 2012 3 ©2012 Integrated Device Technology, Inc.
Table 2. Pin Characteristics
Function Table
Table 3. Control Input Function Table
Symbol Parameter Test Conditions Minimum Typical Maximum Units
R
PULLDOWN
Input Pulldown Resistor 50 k
R
PULLUP
Input Pullup Resistor 50 k
C
IN
Input Capacitance SEL[3:0] 2 pF
Inputs Outputs
SEL3 SEL2 SEL1 SEL0 Q nQ
0 0 0 0 CLK0 nCLK0 (default)
0001CLK1nCLK1
0010CLK2nCLK2
0011CLK3nCLK3
0100CLK4nCLK4
0101CLK5nCLK5
0110CLK6nCLK6
0111CLK7nCLK7
1000CLK8nCLK8
1001CLK9nCLK9
1 0 1 0 CLK10 nCLK10
1 0 1 1 CLK11 nCLK11
11XXL H

853S012AKILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 12:1 Differential 3V,2.5V LVPECL
Lifecycle:
New from this manufacturer.
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