ICS853S012I Data Sheet 12-:1, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL CLOCK/DATA MULTIPLEXER
ICS853S0121AKI REVISION A SEPTEMBER 28, 2012 7 ©2012 Integrated Device Technology, Inc.
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
Measured using a Rohde & Schwarz SMA100 as the input source.
Offset from Carrier Frequency (Hz)
SSB Phase Noise dBc/Hz
Additive Phase Jitter @ 155.52MHz
12kHz to 20MHz = 0.144ps (typical)
ICS853S012I Data Sheet 12-:1, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL CLOCK/DATA MULTIPLEXER
ICS853S0121AKI REVISION A SEPTEMBER 28, 2012 8 ©2012 Integrated Device Technology, Inc.
Parameter Measurement Information
3.3V LVPECL Output Load AC Test Circuit
Differential Input Level
Output Rise/Fall Time
2.5V LVPECL Output Load AC Test Circuit
Part-to-Part Skew
Propagation Delay
SCOPE
Qx
nQx
V
EE
V
CC
2V
-1.3V±0.165V
V
CC
V
EE
V
CMR
Cross Points
V
PP
CLK[0:11]
nCLK[0:11]
nQ
Q
SCOPE
Qx
nQx
V
EE
V
CC
2V
-0.5V±0.125V
tsk(pp)
Part 1
Part 2
nQx
Qx
nQy
Qy
t
PD
nQ
Q
nCLK[0:11]
CLK[0:11]
ICS853S012I Data Sheet 12-:1, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL CLOCK/DATA MULTIPLEXER
ICS853S0121AKI REVISION A SEPTEMBER 28, 2012 9 ©2012 Integrated Device Technology, Inc.
Parameter Measurement Information, continued
MUX Isolation
Input Skew
Amplitude (dB)
A0
Spectrum of Output Signal Q
MUX
_ISOL
= A0 – A1
(fundamental)
Frequency
ƒ
MUX selects other input
MUX selects active
input clock signal
A1
t
PD2
t
PD1
tsk(i) = |t
PD1
- t
PD2
|
tsk(i)
nCLKy
CLKy
nQ
Q
nCLKx
CLKx
x, y = 0 to 11

853S012AKILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 12:1 Differential 3V,2.5V LVPECL
Lifecycle:
New from this manufacturer.
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