FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright©2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2011.7
Memory FRAM
1 M Bit (128 K × 8)
MB85R1001A
DESCRIPTIONS
The MB85R1001A is an FRAM (Ferroelectric Random Access Memory) chip consisting of 131,072
words × 8 bits of nonvolatile memory cells fabricated using ferroelectric process and silicon gate CMOS
process technologies.
The MB85R1001A is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85R1001A can be used for 10
10
read/write operations, which is a significant
improvement over the number of read and write operations supported by Flash memory and E
2
PROM.
The MB85R1001A uses a pseudo-SRAM interface that is compatible with conventional asynchronous SRAM.
FEATURES
Bit configuration : 131,072 words × 8 bits
Read/write endurance : 10
10
times
Operating power supply voltage : 3.0 V to 3.6 V
Operating temperature range : 40 °C to + 85 °C
Data retention : 10 years ( + 55 °C)
Package : 48-pin plastic TSOP (1)
DS501-00003-1v0-E
MB85R1001A
2 DS501-00003-1v0-E
PIN ASSIGNMENTS
PIN DESCRIPTIONS
Pin Number Pin Name Functional Description
1, 2, 4, 5, 8, 18 to 26, 28, 29, 45 A0 to A16 Address Input pins
33 to 35, 38 to 42 I/O1 to I/O8 Data Input/Output pins
44 CE
1 Chip Enable 1 Input pin
7 CE2 Chip Enable 2 Input pin
6WE
Write Enable Input pin
48 OE
Output Enable Input pin
10, 16, 37 VDD
Supply Voltage pins
Connect all three pins to the power supply.
13, 27, 46 VSS
Ground pins
Connect all three pins to ground.
3, 9, 11, 12, 14, 15, 17, 30 to
32, 36, 43, 47
NC No Connect pins
A11
A9
NC
A8
A13
WE
CE2
A15
NC
VDD
NC
NC
VSS
NC
NC
VDD
NC
A16
A14
A12
A7
A6
A5
A4
OE
NC
VSS
A10
CE1
NC
I/O8
I/O7
I/O6
I/O5
I/O4
VDD
NC
I/O3
I/O2
I/O1
NC
NC
NC
A0
A1
VSS
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
(FPT-48P-M48)
(
TOP VIEW)
MB85R1001A
DS501-00003-1v0-E 3
BLOCK DIAGRAM
FUNCTIONAL TRUTH TABLE
Note: L = VIL, H = VIH, X can be either VIL or VIH, Hi-Z = High Impedance
: Latch address and latch data at falling edge, : Latch address and latch data at rising edge
*1 : OE
control of the Pseudo-SRAM means the valid address at the falling edge of OE to read.
*2 : WE
control of the Pseudo-SRAM means the valid address and data at the falling edge of WE to write.
Operation Mode CE1CE2 WE OE I/O1 to I/O8 Supply Current
Standby Precharge
HXXX
Hi-Z
Standby
(I
SB)
XLXX
XXHH
Read
H
HL
Data Output
Operation
(I
CC)
L
Read
(Pseudo-SRAM, OE
control*
1
)
LHH
Write
H
LH
Data Input
L
Write
(Pseudo-SRAM, WE
control*
2
)
LH H
I/O8
I/O1
A0
A16
Address Latch
Row Decoder
FRAM Array
131,072 x 8
Column Decoder
S/A
I/O1 to I/O8
CE2
WE
OE
CE1
intOE
intWE

MB85R1001ANC-GE1

Mfr. #:
Manufacturer:
Fujitsu
Description:
IC FRAM 1M PARALLEL 48TSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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