17
LTC1408-12
140812f
APPLICATIO S I FOR ATIO
WUUU
used to drive the serial port interface. Also note that the
master clock in the DSP may already be corrupted with
jitter, even if it comes directly from the DSP crystal.
Another problem with high speed processor clocks is that
they often use a low cost, low speed crystal (i.e., 10MHz)
to generate a fast, but jittery, phase-locked-loop system
clock (i.e., 40MHz). The jitter in these PLL-generated high
speed clocks can be several nanoseconds. Note that if you
choose to use the frame sync signal generated by the DSP
port, this signal will have the same jitter of the DSP’s
master clock.
The Typical Application Figure on page 20 shows a circuit
for level-shifting and squaring the output from an RF
signal generator or other low-jitter source. A single D-type
flip flop is used to generate the CONV signal to the
LTC1408-12. Re-timing the master clock signal eliminates
clock jitter introduced by the controlling device (DSP,
FPGA, etc.) Both the inverter and flip flop must be treated
as analog components and should be powered from a
clean analog supply.
Serial Clock Input (SCK)
The rising edge of SCK advances the conversion process
and also udpates each bit in the SDO data stream. After
CONV rises, the third rising edge of SCK sends out up to
six sets of 12 data bits, with the MSB sent first. A simple
approach is to generate SCK to drive the LTC1408-12 first
and then buffer this signal with the appropriate number of
inverters to drive the serial clock input of the processor
serial port. Use the falling edge of the clock to latch data
from the Serial Data Output (SDO) into your processor
serial port. The 12-bit Serial Data will be received in six
16-bit words with 96 or more clocks per frame sync. If
fewer than 6 channels are selected by SEL0–SEL2 for
conversion, then 16 clocks are needed per channel to
convert the analog inputs and read out the resulting data
after the next convert pulse. It is good practice to drive the
LTC1408-12 SCK input first to avoid digital noise interfer-
ence during the internal bit comparison decision by the
internal high speed comparator. Unlike the CONV input,
the SCK input is not sensitive to jitter because the input
signal is already sampled and held constant.
Serial Data Output (SDO)
Upon power-up, the SDO output is automatically reset
to the high impedance state. The SDO output remains
in high impedance until a new conversion is started.
SDO sends out up to six sets of 12 bits in the output data
stream after the third rising edge of SCK after the start
of conversion with the rising edge of CONV. The six or
fewer 12-bit words are separated by two don’t care bits
and two clock cycles in high impedance mode. Please
note the delay specification from SCK to a valid SDO.
SDO is always guaranteed to be valid by the next rising
edge of SCK. The 16 – 96-bit output data stream is
compatible with the 16-bit or 32-bit serial port of most
processors.
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolu-
tion and/or high speed A/D converters. To obtain the best
performance from the LTC1408-12, a printed circuit board
with ground plane is required. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track. If optimum phase match between the
inputs is desired, the length of the twelve input wires of the
six input channels should be kept matched. But each pair
of input wires to the six input channels should be kept
separated by a ground trace to avoid high frequency
crosstalk between channels.
