OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

LTC1408CUH-12#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
7
LTC1408-12
140812f
UU
U
PI FU CTIO S
SDO (Pin 1): Three-State Serial Data Output. Each set of
six output data words represent the six analog input
channels at the start of the previous conversion. Data for
CH0 comes out first and data for CH5 comes out last. Each
data word comes out MSB first.
OGND (Pin 2): Ground Return for SDO Currents. Connect
to the solid ground plane.
OV
DD
(Pin 3): Power Supply for the SDO Pin. OV
DD
must
be no more than 300mV higher than V
DD
and can be
brought to a lower voltage to interface to low voltage logic
families. The unloaded high state at SDO is at the potential
of OV
DD
.
CH0
+
(Pin 4): Non-Inverting Channel 0. CH0
+
operates
fully differentially with respect to CH0
–
with a 0V to 2.5V,
or ±1.25V differential swing and a 0V to V
DD
absolute
input range.
CH0
–
(Pin 5): Inverting Channel 0. CH0
–
operates fully
differentially with respect to CH0
+
with a –2.5V to 0V,
or ±1.25V differential swing and a 0V to V
DD
absolute
input range.
GND (Pins 6, 9, 12, 13, 16, 19): Analog Grounds. These
ground pins must be tied directly to the solid ground plane
under the part. Analog signal currents flow through these
connections.
CH1
+
(Pin 7): Non-Inverting Channel 1. CH1
+
operates
fully differentially with respect to CH1
–
with a 0V to 2.5V,
or ±1.25V differential swing and a 0V to V
DD
absolute
input range.
CH1
–
(Pin 8): Inverting Channel 1. CH1
–
operates fully
differentially with respect to CH1
+
with a –2.5V to 0V,
or ±1.25V differential swing and a 0V to V
DD
absolute
input range.
CH2
+
(Pin 10): Non-Inverting Channel 2. CH2
+
operates
fully differentially with respect to CH2
–
with a 0V to 2.5V,
or ±1.25V differential swing and a 0V to V
DD
absolute
input range.
CH2
–
(Pin 11): Inverting Channel 2. CH2
–
operates fully
differentially with respect to CH2
+
with a –2.5V to 0V, or
±1.25V differential swing and a 0V to V
DD
absolute
input range.
CH3
+
(Pin 14): Non-Inverting Channel 3. CH3
+
operates
fully differentially with respect to CH3
–
with a 0V to 2.5V,
or ±1.25V differential swing and a 0V to V
DD
absolute
input range.
CH3
–
(Pin 15): Inverting Channel 3. CH3
–
operates fully
differentially with respect to CH3
+
with a –2.5V to 0V, or
±1.25V differential swing and a 0V to V
DD
absolute
input range.
CH4
+
(Pin 17): Non-Inverting Channel 4. CH4
+
operates
fully differentially with respect to CH4
–
with a 0V to 2.5V,
or ±1.25V differential swing and a 0V to V
DD
absolute input
range.
CH4
–
(Pin 18): Inverting Channel 4. CH4
–
operates fully
differentially with respect to CH4
+
with a –2.5V to 0V, or
±1.25V differential swing and a 0V to V
DD
absolute input
range.
CH5
+
(Pin 20): Non-Inverting Channel 5. CH5
+
operates
fully differentially with respect to CH5
–
with a 0V to 2.5V,
or ±1.25V differential swing and a 0V to V
DD
absolute input
range.
CH5
–
(Pin 21): Inverting Channel 5. CH5
–
operates fully
differentially with respect to CH5
+
with a –2.5V to 0V, or
±1.25V differential swing and a 0V to V
DD
absolute input
range.
GND (PIN 22): Analog Ground for Reference. Analog
ground must be tied directly to the solid ground plane
under the part. Analog signal currents flow through this
connection. The 10µF reference bypass capacitor should
be returned to this pad.
V
REF
(Pin 23): 2.5V Internal Reference. Bypass to GND
and a solid analog ground plane with a 10µF ceramic
capacitor (or 10µF tantalum in parallel with 0.1µF ce-
ramic). Can be overdriven by an external reference voltage
between 2.55V and V
DD
, V
CC
.
V
CC
(Pin 24): 3V Positive Analog Supply. This pin supplies
3V to the analog section. Bypass to the solid analog
ground plane with a 10µF ceramic capacitor (or 10µF
tantalum) in parallel with 0.1µF ceramic. Care should be
taken to place the 0.1µF bypass capacitor as close to
Pin 24 as possible. Pin 24 must be tied to Pin 25.
8
LTC1408-12
140812f
V
DD
(Pin 25): 3V Positive Digital Supply. This pin supplies
3V to the logic section. Bypass to DGND pin and solid
analog ground plane with a 10µF ceramic capacitor (or
10µF tantalum in parallel with 0.1µF ceramic). Keep in
mind that internal digital output signal currents flow
through this pin. Care should be taken to place the 0.1µF
bypass capacitor as close to Pin 25 as possible. Pin 25
must be tied to Pin 24.
SEL2 (Pin 26): Most significant bit controlling the
number of channels being converted. In combination with
SEL1 and SEL0, 000 selects just the first channel (CH0) for
conversion. Incrementing SELx selects additional
channels(CH0–CH5) for conversion. 101, 110 or 111
select all 6 channels for conversion. Must be kept in a fixed
state during conversion and during the subsequent con-
version to read data.
SEL1 (Pin 27): Middle significance bit controlling the
number of channels being converted. In combination with
SEL0 and SEL2, 000 selects just the first channel (CH0) for
conversion. Incrementing SELx selects additional
channels for conversion. 101, 110 or 111 select all 6
channels (CH0–CH5) for conversion. Must be kept in a
fixed state during conversion and during the subsequent
conversion to read data.
SEL0 (Pin 28): Least significant bit controlling the
number of channels being converted. In combination with
SEL1 and SEL2, 000 selects just the first channel (CH0) for
conversion. Incrementing SELx selects additional
channels for conversion. 101, 110 or 111 select all 6
channels (CH0–CH5) for conversion. Must be kept in a
fixed state during conversion and during the subsequent
conversion to read data.
UU
U
PI FU CTIO S
BIP (Pin 29): Bipolar/Unipolar Mode. The input differen-
tial range is 0V – 2.5V when BIP is LOW, and it is ±1.25V
when BIP is HIGH. Must be kept in fixed state during
conversion and during subsequent conversion to read
data. When changing BIP between conversions the full
acquisition time must be allowed before starting the next
conversion. The output data is in 2’s complement
format for bipolar mode and straight binary format for
unipolar mode.
CONV (Pin 30): Convert Start. Holds the six analog input
signals and starts the conversion on CONV’s rising edge.
Two CONV pulses with SCK in fixed high or fixed low state
starts Nap mode. Four or more CONV pulses with SCK in
fixed high or fixed low state starts Sleep mode.
DGND (Pin 31): Digital Ground. This ground pin must be
tied directly to the solid ground plane. Digital input signal
currents flow through this pin.
SCK (Pin 32): External Clock Input. Advances the conver-
sion process and sequences the output data at SD0 (Pin1)
on the rising edge. One or more SCK pulses wake from
sleep or nap power saving modes. 16 clock cycles are
needed for each of the channels that are activated by SELx
(Pins 26, 27, 28), up to a total of 96 clock cycles needed
to convert and read out all 6 channels.
EXPOSED PAD (Pin 33): GND. Must be tied directly to the
solid ground plane.
9
LTC1408-12
140812f
BLOCK DIAGRA
W
2
OGND
1
SD0
3
OV
DD
3V
–
+
4
5
24
23
S & H
–
+
7
6
9
12 13
16
19
8
S & H
GND
EXPOSED PAD
V
REF
10µF
CH0
–
CH0
+
CH1
–
CH1
+
–
+
10
11
S & H
–
+
14
15
S & H
CH2
–
CH2
+
CH3
–
CH3
+
–
+
17
18
S & H
–
+
20
21
S & H
CH4
–
CH4
+
CH5
–
CH5
+
10µF
0.1µF
DGND
32
SCK
30
CONV
SEL2
SEL1
SEL0
THREE-
STATE
SERIAL
OUTPUT
PORT
MUX
2.5V
REFERENCE
TIMING
LOGIC
V
CC
25
3V
V
DD
1408 BD
600ksps
12-BIT ADC
12-BIT LATCH 5
12-BIT LATCH 4
12-BIT LATCH 3
12-BIT LATCH 2
12-BIT LATCH 1
12-BIT LATCH 0
26
27
BIP
29
28 31
2233
0.1µF
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

LTC1408CUH-12#TRPBF

Mfr. #:
Buy LTC1408CUH-12#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 6 Ch, 12-B, 600ksps Simultaneous Smpl AD
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet