Functional Description 15
January 11, 2017
82V3155 ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
2.7.3 LOOP FILTER
The Loop Filter ensures that the jitter transfer meets the ETS 300
011 and AT&T TR62411 requirements. It works similarly to a first order
low pass filter with 2.1 Hz cutoff frequency for the four valid input
frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz).
The output of the Loop Filter goes to the Digital Control Oscillator
directly or through the Fraction blocks, in which E1, T1, C6 and C19
signals are generated.
2.7.4 FRACTION BLOCK
By applying some algorithms to the incoming E1 signal, the
Fraction_C19, Fraction_C6 and Fraction_T1 blocks generate C19, C6
and T1 signals respectively.
2.7.5 DIGITAL CONTROL OSCILLATOR (DCO)
In the Normal mode, the DCO receives four limited and filtered
signals from Loop Filter or Fraction blocks. Based on the values of the
received signals, the DCO generates four digital outputs: 19.44 MHz,
25.248 MHz, 32.768 MHz and 24.704 MHz for C19, C6, E1 and T1
dividers respectively.
In the Holdover mode, the DCO is running at the same frequency as
that generated by storage techniques.
In the Freerun mode, the DCO is running at the same frequency as
that of the master clock.
2.7.6 LOCK INDICATOR
If the output frequency of the DPLL is identical to the input frequency,
and the input phase offset is small enough so that no slope limiting is
exhibited, the LOCK pin will be set high.
2.7.7 OUTPUT INTERFACE
The Output Interface uses three output signals from the DCO to
generate totally 10 types of clock signals and 7 types of framing signals
All these output signals are synchronous to F8o.
The 32.768 MHz signal is used by the E1_divider to generate 5 types
of clock signals (C2o, C4o, C8o, C16o and C32o) with nominal 50% duty
cycle and 6 types of framing signals (F0o, F8o, F16o, F32o, RSP and
TSP).
The 24.704 MHz signal is used by the T1_divider to generate two
types of T1 signals (C1.5o and C3o) with nominal 50% duty cycle.
The 25.248 MHz signal is used by the C6_divider to generate a C6o
signal with nominal 50% duty cycle.
The 19.44 MHz signal is sent to an APLL, which outputs a 155.52
MHz signal. The 155.52 MHz signal is used by the C19_divider to
generate 19.44 MHz and 155.52 MHz clock signals (C19o, C155POS
and C155NEG) with nominal 50% duty cycle and a framing signal F19o.
Additionally, the IDT82V3155 provides an output clock (C2/C1.5)
with the frequency controlled by the frequency selection pins Fx_sel0
and Fx_sel1 (see Table - 5 for details). If the selected reference input
(Fref0 or Fref1) is 8 kHz, 2.048 MHz or 19.44 MHz, the C2/C1.5 pin will
output a 2.048 MHz clock signal. If the selected reference input (Fref0 or
Fref1) is 1.544 MHz, the C2/C1.5 pin will output a 1.544 MHz clock
signal. The electrical and timing characteristics of this output (2.048
MHz or 1.544 MHz) is the same as that of C2o or C1.5o.
Table - 5 C2/C1.5 Output Frequency Control
Frequency Selection Pins
Frefx Input
Frequency
C2/C1.5 Output
Frequency
Fx_sel1 Fx_sel0
0 0 19.44 MHz 2.048 MHz
0 1 8 kHz 2.048 MHz
1 0 1.544 MHz 1.544 MHz
1 1 2.048 MHz 2.048 MHz
Note: ‘x’ can be 0 or 1, as selected by IN_sel pin.
IN_sel = 0: x = 0, Fref0 is the selected reference input. The frequency of Fref0
is determined by F0_sel0 and F0_sel1 pins.
IN_sel = 1: x = 1, Fref1 is the selected reference input. The frequency of Fref1
is determined by F1_sel0 and F1_sel1 pins.
