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CY7C1021BNV33L-15ZXIT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
Timing Characteristics 31
January 11, 2017
82V3155 ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
Figure - 12 Input to Output Timing (Normal Mode)
t
R8D
t
RW
t
R15D
t
RW
Fref0/Fref1
8 kHz
Fref0/Fref1
1.544 MHz
Fref0/Fref1
2.048 MHz
F8o
Fref0/Fref1
19.44 MHz
t
R2D
t
RW
t
RW
t
R19D
V
T
V
T
V
T
V
T
V
T
Timing Characteristics 32
January 11, 2017
82V3155 ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
Figure - 13 Output Timing 1
t
F8WH
t
F0D
t
F0WL
t
F16D
t
F16WL
t
F16H
t
F16S
t
C16D
t
C16W
t
C8W
t
C4W
t
C2W
t
C2D
t
C6W
t
C6D
t
C15D
t
C15W
t
C8D
t
C4D
V
T
V
T
V
T
V
T
V
T
V
T
V
T
V
T
V
T
C1.5o
C6o
C2o
C4o
C8o
C16o
F16o
F0o
F8o
C32o
C3o
t
C32D
t
C3D
t
C3W
t
C32WH
V
T
V
T
F32o
t
F32WL
t
F32D
V
T
t
F32S
t
F32H
t
C6W
t
C4W
t
C8W
V
T
C19o
C155
0
t
C19D
t
C19W
V
T
t
F19WH
t
F19D
t
F19S
t
F19H
F19o
t
C155W
t
C155D
(see Note 1)
(see Note 1)
V
DD
Timing Characteristics 33
January 11, 2017
82V3155 ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
Figure - 14 Output Timing 2
Note 1: The timing characteristic of C2/C1.5 (2.048 MHz or 1.544 MHz) is the same as that of C2o or C1.5o.
Figure - 15 Input Control Setup and Hold Timing
F8o
C2o
RSP
TSP
t
RSPD
t
RSPW
t
TSPD
t
TSPW
V
T
V
T
V
T
V
T
V
T
V
T
t
H
t
S
F8o
MODE_sel0
MODE_sel1
TIE_en
IN_sel
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34

CY7C1021BNV33L-15ZXIT

Mfr. #:
Buy CY7C1021BNV33L-15ZXIT
Manufacturer:
Cypress Semiconductor
Description:
SRAM 2Mb 15ns 3.3V 64Kx16 Fast Async SRAM
Lifecycle:
New from this manufacturer.
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