RT9010-12GJ6

RT9010
7
DS9010-05 April 2011 www.richtek.com
Start Up
Time (5μs/Div)
RT9010-28, V
IN
= 5V
I
OUT
= 50mA
(5V/Div)
(1V/Div)
V
EN
V
OUT
Power-On
Time (10μs/Div)
RT9010-28
I
LOAD
= 10mA
V
EN
(5V/Div)
V
OUT
(2V/Div)
POR
(5V/Div)
Noise
Time (10ms/Div)
RT9010-33, No LOAD
V
IN
= V
EN
= 4.5V(By battery)
C
IN
= C
OUT
= 1uF/X7R
Noise (μV/Div)
150
100
50
0
-50
-100
-150
EN Pin Shutdown Response
Time (50μs/Div)
RT9010-28, V
IN
= 5V
I
OUT
= 50mA
(5V/Div)
(1V/Div)
V
EN
V
OUT
Time (10ms/Div)
RT9010-33, I
LOAD
= 50mA
V
IN
= V
EN
= 4.5V(By battery)
C
IN
= C
OUT
= 1uF/X7R
Noise (μV/Div)
300
200
100
0
-100
-200
-300
Noise
RT9010
8
DS9010-05 April 2011www.richtek.com
Applications Information
Like any low-dropout regulator, the external capacitors used
with the RT9010 must be carefully selected for regulator
stability and performance. Using a capacitor whose value
is > 1μF on the RT9010 input and the amount of
capacitance can be increased without limit. The input
capacitor must be located a distance of not more than 0.5
inch from the input pin of the IC and returned to a clean
analog ground. Any good quality ceramic or tantalum can
be used for this capacitor. The capacitor with larger value
and lower ESR (equivalent series resistance) provides
better PSRR and line-transient response.
The output capacitor must meet both requirements for
minimum amount of capacitance and ESR in all LDOs
application. The RT9010 is designed specifically to work
with low ESR ceramic output capacitor in space-saving
and performance consideration. Using a ceramic capacitor
whose value is at least 1μF with ESR is > 20mΩ on the
RT9010 output ensures stability. The RT9010 still works
well with output capacitor of other types due to the wide
stable ESR range. Figure 1. shows the curves of allowable
ESR range as a function of load current for various output
capacitor values. Output capacitor of larger capacitance
can reduce noise and improve load transient response,
stability, and PSRR. The output capacitor should be located
not more than 0.5 inch from the VOUT pin of the RT9010
and returned to a clean analog ground.
Figure 1. Stable Cout ESR Range
V
OUT
Short to GND
0.4V
V
OUT
I
OUT
TSD
OTP Trip Point
170 C
°
110 C
°
110 C
°
80 C
°
IC Temperature
Figure 2. Short Circuit Thermal Folded Back Protection
when Output Short Circuit Occurs (Patent)
For continuous operation, do not exceed absolute
maximum operation junction temperature 125°C. The
power dissipation definition in device is :
P
D
= (V
IN
V
OUT
) x I
OUT
+ V
IN
x I
Q
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by following formula :
P
D(MAX)
= ( T
J(MAX)
T
A
) /θ
JA
Where T
J(MAX)
is the maximum operation junction
temperature 125°C, T
A
is the ambient temperature and the
θ
JA
is the junction to ambient thermal resistance.
Thermal Considerations
Thermal protection limits power dissipation in RT9010.
When the operation junction temperature exceeds 170°C,
the OTP circuit starts the thermal shutdown function and
turns the pass element off. The pass element turn on again
after the junction temperature cools by 40°C. RT9010
lowers its OTP trip level from 170°C to 110°C when output
short circuit occurs (V
OUT
< 0.4V) as shown in Figure 2. It
limits IC case temperature under 100°C and provides
maximum safety to customer while output short circuit
occurring.
Region of Stable C
OUT
ESR vs. Load Current
0.001
0.01
0.1
1
10
100
0 50 100 150 200 250 300
Load Current (mA)
Region of Stable C
OUT
ESR ()
Region of Stable C
OUT
ESR (Ω)
Unstable Region
Stable Region
Simulation Verify Unstable Region
RT9010-28, V
IN
= 5V
C
IN
= 1uF/X7R
RT9010
9
DS9010-05 April 2011 www.richtek.com
Figure 3. Derating Curves for RT9010 Packages
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0 25 50 75 100 125
Ambient Temperature
Power Dissipation (W)
(°C)
TSOT-23-6
For recommended operating conditions specification of
RT9010, where T
J(MAX)
is the maximum junction
temperature of the die (125°C) and T
A
is the operated
ambient temperature. The junction to ambient thermal
resistance (θ
JA
is layout dependent) for TSOT-23-6 package
is 220°C/W on the standard JEDEC 51-3 single-layer
thermal test board. The maximum power dissipation at
T
A
= 25°C can be calculated by following formula :
P
D(MAX)
= ( 125°C - 25°C) / (220°C/W) = 0.455 W for
TSOT-23-6 packages
The maximum power dissipation depends on operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance θ
JA
. For RT9010 packages, the Figure 3 of de-
rating curves allows the designer to see the effect of rising
ambient temperature on the maximum power allowed.

RT9010-12GJ6

Mfr. #:
Manufacturer:
Description:
IC REG LIN 1.2V 300MA TSOT23-6
Lifecycle:
New from this manufacturer.
Delivery:
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