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LTC3607EMSE#PBF

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LTC3607
10
3607fb
For more information www.linear.com/LTC3607
applicaTions inForMaTion
Input Capacitor (C
IN
) Selection
In continuous mode, the input current of the converter is a
square wave with a duty cycle of approximately V
OUT
/V
IN
.
To prevent large voltage transients, a low equivalent series
resistance (ESR) input capacitor sized for the maximum
RMS current must be used. The maximum RMS capacitor
current is given by:
I
RMS
≈I
OUT(MAX)
V
OUT
(V
IN
– V
OUT
)
V
IN
where the maximum average output current I
MAX
equals
the peak current minus half the peak-to-peak ripple cur-
rent, I
MAX
= I
LIM
– ΔI
L
/2.
This formula has a maximum at V
IN
= 2V
OUT
, where I
RMS
= I
OUT
/2. This simple worst-case is commonly used to
design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple cur
-
rent ratings are often based on only 2000 hours lifetime.
This makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to meet
the size or height requirements of the design. An additional
0.1μF to 1μF ceramic capacitor is also recommended on
V
IN
for high frequency decoupling, when not using an all
ceramic capacitor solution.
Output Capacitor (C
OUT
) Selection
The selection of C
OUT
is driven by the required ESR to
minimize voltage ripple and load step transients. Typically,
once the ESR requirement is satisfied, the capacitance
is adequate for filtering. The output ripple (ΔV
OUT
) is
determined by:
V
OUT
≈∆ ∆I
L
ESR+
1
8f
O
C
OUT
where f
O
= operating frequency, C
OUT
= output capacitance
and ΔI
L
= ripple current in the inductor. The output ripple
is highest at maximum input voltage since ΔI
L
increases
with input voltage. With ΔI
L
= 240mA the output ripple will
be less than 100mV at maximum V
IN
and f
O
= 2.25MHz
with: ESR
COUT
< 150mΩ.
Once the ESR requirements for C
OUT
have been met, the
RMS current rating generally far exceeds the I
RIPPLE(P-P)
requirement, except for an all ceramic solution.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation and the
output capacitor size. Typically, 3 to 4 cycles are required
to respond to a load step, but only in the first cycle does
the output drop linearly. The output droop, V
DROOP
, is
usually about five times the linear drop of the first cycle.
Thus, a good place to start is with the output capacitor
size of approximately:
C
OUT
≈5
∆I
OUT
f
O
• V
DROOP
Though this equation provides a good approximation, more
capacitance may be required depending on the duty cycle
and load step requirements.
Ceramic Input and Output Capacitors
High value, low cost ceramic capacitors are available in
small case sizes. Their high ripple current, high voltage
rating, and low ESR make them ideal for switching regulator
applications. However, due to the self-resonant and high-Q
characteristics of some types of ceramic capacitors, care
must be taken when these capacitors are used at the input.
When a ceramic capacitor is used at the input and the power
is being supplied through long wires, such as from a wall
adapter, a load step at the output can induce ringing at
the V
IN
pin. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, the ringing
at the input can be large enough to damage the part. For
a more detailed discussion, refer to Application Note 88.
LTC3607
11
3607fb
For more information www.linear.com/LTC3607
applicaTions inForMaTion
Setting the Output Voltage
The LTC3607 develops a 0.6V reference voltage between
the feedback pins, V
FB1
and V
FB2
, and ground as shown
in Figure 1. The output voltage is set by a resistive divider
according to the following formula:
V
OUT
=0.6V 1+
R1
R2
Keeping the current small (<5μA) in these resistors maxi-
mizes efficiency, but making them too small may allow
stra
y capacitance to cause noise problems and reduce
the phase margin of the error amp loop.
To improve the frequency response, a feed-forward ca
-
pacitor C
FF
may also be used. Great care should be taken
to route the V
FB
traces away from noise sources, such as
the inductor or the SW traces.
For continuous mode operation with a fixed maximum
input voltage, the minimum value that the output voltage
can be reduced to is set by the minimum on-time, which
is approximately 65ns. For fixed frequency (2.25MHz) ap
-
plications, the relation between minimum output voltage
and maximum input voltage is:
V
OUT(MIN)
= 0.14625 • V
IN(MAX)
If the output voltage drops below that limit, the output will
still regulate, but the part will skip cycles.
Power Good Outputs
The PGOOD1 and PGOOD2 are open-drain outputs which
pull low when a regulator is out of regulation. When the
output voltage is within ±8.5% of regulation, a timer is
started which releases the relevant PGOOD pin after 64
clock cycles.
Mode Selection & Frequency Synchronization
The MODE/SYNC pin is a multipurpose pin which provides
mode selection and frequency synchronization. Floating
this pin or connecting it to a 3.3V source enables Burst Mode
operation, which provides optimal light load efficiency at
the cost of a slightly higher output voltage ripple. When
this pin is connected to ground, pulse-skipping operation
is selected. This mode provides the lowest output ripple,
at the cost of slightly lower light load efficiency.
The LTC3607 can also be synchronized to another LTC3607
by the MODE/SYNC pin. During synchronization, the
mode is set to pulse-skipping and the top switch turn-on
is synchronized to the rising edge of the external clock.
Pulse-skipping mode is also the default mode during
start-up.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to ΔI
LOAD
• ESR, where ESR is the effective series
resistance of C
OUT
. ΔI
LOAD
also begins to charge or dis-
charge C
OUT
generating a feedback error signal used by the
regulator to return V
OUT
to its steady-state value. During
this recovery time, V
OUT
can be monitored for overshoot
or ringing that would indicate a stability problem.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phase margin. In addition, a feed-forward capacitor can be
added to improve the high frequency response, as shown
in Figure 1. Capacitors C1 and C2 provide phase lead by
creating high frequency zeros with R1 and R3 respectively,
which improve the phase margin.
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
In some applications, a more severe transient can be caused
by switching in loads with large (>1μF) input capacitors.
The discharged input capacitors are effectively put in paral
-
lel with C
OUT
, causing a rapid drop in V
OUT
. No regulator
can deliver enough current to prevent this problem if the
switch connecting the load has low resistance and is driven
quickly. The solution is to limit the turn-on speed of the
load switch driver. A Hot Swap™ controller is designed
specifically for this purpose and usually incorporates cur
-
rent limiting, short-circuit protection, and soft-starting.
LTC3607
12
3607fb
For more information www.linear.com/LTC3607
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% - (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent
-
age of input power. Although all dissipative elements in
the circuit produce losses, four main sources usually
account for most of the losses in LTC3607 circuits: 1)
V
IN
quiescent current, 2) switching losses, 3) I
2
R losses,
4) other losses.
1) The V
IN
current is the DC supply current given in the
Electrical Characteristics which excludes MOSFET driver
and control currents. V
IN
current results in a small loss
that increases with V
IN
, even at no load.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results
from switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high
to low again, a packet of charge dQ moves from V
IN
to
ground. The resulting dQ/dt is a current out of V
IN
that is
typically much larger than the DC bias current. In continu-
ous mode, I
GATECHG
= f
O
(Q
T
+ Q
B
), where Q
T
and Q
B
are
the gate charges of the internal top and bottom MOSFET
switches. The gate charge losses are proportional to V
IN
and thus their effects will be more pronounced at higher
supply voltages.
3) I
2
R losses are calculated from the DC resistances of
the internal switches, R
SW
, and external inductor, R
L
. In
continuous mode, the average output current flows through
inductor L, but is chopped between the internal top and
bottom switches. Thus, the series resistance looking into
the SW pin is a function of both top and bottom MOSFET
R
DS(ON)
and the duty cycle (D) as follows:
R
SW
= (R
DS(ON)TOP
)(D) + (R
DS(ON)BOT
)(1 – D)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. Thus, to obtain I
2
R losses:
I
2
R losses = I
OUT
2
(R
SW
+ R
L
)
4) Other hidden losses such as copper trace and internal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important to
include these system level losses in the design of a system.
The internal battery and fuse resistance losses can be
minimized by making sure that C
IN
has adequate charge
storage and very low ESR at the switching frequency.
Other losses including diode conduction losses during
dead-time and inductor core losses generally account for
less than 2% total additional loss.
Thermal Considerations
In a majority of applications, the LTC3607 does not dis
-
sipate much heat due to its high efficiency. However, in
appl
ications where the LTC3607 is running at high ambient
temperature with low supply voltage and high duty cycles,
such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both power
switches for each channel will be turned off and the SW
nodes will become high impedance.
To prevent the LTC3607 from exceeding the maximum
junction temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise
is given by:
T
RISE
= P
D
• θ
JA
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, T
J
, is given by:
T
J
= T
RISE
+ T
AMBIENT
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LTC3607EMSE#PBF

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Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 15V Dual 600mA Monolithic Synchronous Step-Down DC/DC Regulator
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