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NCP1215DR2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
NCP1215
http://onsemi.com
7
APPLICATION INFORMATION
The NCP1215 implements a current mode SMPS with a
variable OFF−time dependant upon output power demand.
It can be seen from the typical application that NCP1215 is
designed to operate with a minimum number of external
component. The NCP1215 incorporates the following
features:
• Frequency Foldback: Since the switch−off time
increases when power demand decreases, the switching
frequency naturally diminishes in light load conditions.
This helps to minimize switching losses and offers
excellent standby power performance.
• Very Low Startup Current: The patented internal
supply block is specially designed to offer a very low
current consumption during startup. It allows the use of
a very high value external startup resistor, greatly
reducing dissipation, improving efficiency and
minimizing standby power consumption.
• Natural Frequency Dithering: The quasi−fixed T
on
mode of operation improves the EMI signature since
the switching frequency varies with the natural bulk
ripple voltage.
• Peak Current Compression: As the load becomes
lighter, the frequency decreases and can enter the
audible range. To avoid exciting transformer
mechanical resonances, hence generating acoustic
noise, the NCP1215 includes a patented technique,
which reduces the peak current as power goes down.
As such, inexpensive transformer can be used without
having noise problems.
• Negative Primary Current Sensing: By sensing
the total current, this technique does not modify the
MOSFET driving voltage (Vgs) while switching.
Furthermore, the programming resistor together with the
pin capacitance, forms a residual noise filter which
blanks spurious spikes. Also fixing primary current level
to a maximum value sets the maximum power limit.
• Programmable Primary Current Sense: It offers a
second peak current adjustment variable which improves
the design flexibility.
• Secondary or Primary Regulation: The feedback
loop arrangement allows simple secondary or primary
side regulation without significant additional external
components.
A detailed description of each internal block within the IC
is given in the following.
Feedback Loop Control
The main task of the Feedback Loop Block is to control
the SMPS output voltage through the change of primary
switch OFF time interval. It sets the peak voltage of the
timing capacitor, which varies upon the output power
demand. Figure 13 shows the simplified internal schematic:
Figure 13. Feedback Loop − OFF Time Control
FB
17 k
Current
Mirror
1:1
Current
Mirror
1:1
−
+
To OFF
Time
Comparator
45 k
V
offset
V
CC
The voltage feedback signal is sensed as a current injected
through the FB pin.
Figure 14. FB Loop Transfer Characteristic
OFF−Time Comparator Input Voltage
V
DD
V
offset
0 mA
FB Pin Sink Current
The transfer characteristic (output voltage to input
current) of the feedback loop control block can be seen in
Figure 14. V
DD
refers to the internal stabilized supply
whereas the offset value sets the maximum switching
frequency in lack of optocoupler current (e.g. an output
short−circuit).
To keep the switching frequency above the audio range in
light load condition the FB pin also regulates in certain range
the peak primary current. The corresponding block diagram
can be seen from Figure 15.
NCP1215
http://onsemi.com
8
Figure 15. Feedback Loop − Current Sense Control
FB
17 k
Current
Mirror
4:3
37.5 mA 12.5 mA
CS
To Current Sense Comparator
The resulting current sense regulation characteristic can
be seen from Figure 16.
Figure 16. Current Sense Regulation Characteristic
CS Pin Source Current
1
2.5 mA
50 mA
140 m
A
100 mA50 mA0 mA
FB Pin Sink Current
When the load goes light, the compression circuitry
decreases the peak current. This has the effect of slightly
increasing the switching frequency but the compression
ratio is selected to not hamper the standby power.
OFF Time Control
The loop signal together with the internal current source,
via an external capacitor, controls the switch−off time. This
is portrayed in Figure 17.
Figure 17. OFF Time Control
−
+
+
−
CT
Voffset
10 mA
From Feedback Loop Block
V
offset
to V
DD
To Latch’s Set Input
To Latch’s Output
GND
CT
During the switch−ON time, the CT capacitor is kept
discharged by a MOSFET switch. As soon as the latch
output changes to a low state, the voltage across CT created
by the internal current source, starts to ramp−up until its
value reaches the threshold given by the feedback loop
demand.
Figure 18. CT Pin Voltage (P
out
1 u P
out
2 u P
out
3)
V
offset
V
DD
V
CT Pin
Voltage
P
OUT
Goes Down
P
OUT
Goes Up
t
off−min
t
P3
P2
P1
The voltage that can be observed on CT pin is shown in
Figure 18. The bold waveform shows the maximum output
power when the OFF time is at its minimum. The IC allows
an OFF time of several seconds.
NCP1215
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9
Primary Current Sensing
The primary current sensing circuit is shown in Figure 19.
CS
R
shift
V
shift
R
CS
V
CS
GND
+
−
To Latch
I
primary
Figure 19. Primary Current Sensing
12.5 mA
B
50 mA
Feedback Loop
Control
FB
When the primary switch is ON, the transformer current
flows through the sense resistor R
cs
. The current creates a
voltage, V
cs
which is negative with respect to GND. Since
the comparator connected to CS pin requires a positive
voltage, the voltage V
shift
is developed across the resistor
R
shift
by a current source which level−shifts the negative
voltage V
cs
. The level−shift current is in range from 12.5 to
50 mA depending on the Feedback Loop Control block
signal (see more details in the Feedback Loop Control
section).
The peak primary current is thus equal to:
I
pk
+
R
shift
R
CS
·I
CS
(eq. 1)
A typical CS pin voltage waveform is shown in Figure 20.
Figure 20. CS Pin Voltage
0
tSwitch
Turn−on
I
shift
= 12.5 mA
I
shift
= 50 mA
V
Figure 20 also shows the effect of the inductor current of
differing output power demand.
The primary current sensing method we described, brings
the following benefits compared to the traditional approach:
• Maximum peak voltage across the current sense resistor
is determined and can be optimized by the value of the
shift resistor.
• CS pin is not exposed to negative voltage, which could
induce a parasitic substrate current within the IC and
distort the surrounding internal circuitry.
• The gate drive capability is improved because the
current sense resistor is located out of the gate driver
loop and does not deteriorate the turn−on and also
turn−off gate drive amplitude.
Gate Driver
The Gate Driver consists of a CMOS buffer designed to
directly drive a power MOSFET.
It features an unbalanced source and sink capabilities to
optimize turn ON and OFF performance without additional
external components. Since the power MOSFET turns−off
at high drain current, to minimize its turn−off losses the sink
capability of the gate driver is increased for a faster turn−off.
To the opposite, the source capability is lower to slow−down
power MOSFET at turn−on in order to reduce the EMI noise.
Whenever the IC supply voltage is lower than the
undervoltage threshold, the Gate Driver is low, pulling down
the gate to ground. It eliminates the need for an external
resistor.
Startup Circuit
An external startup resistor is connected between high
voltage potential of the input bulk capacitor and Vcc supply
capacitor. The value of the resistor can be calculated as
follows:
R
startup
+
V
bulk
* V
startup
I
startup
(eq. 2)
Where:
V
startup
V
cc
voltage at which IC starts operation
(see spec.)
I
startup
Startup current
V
bulk
Input bulk capacitor’s voltage
Since the V
bulk
voltage has obviously much higher value
than V
startup
the equation can be simplified in the following
way:
R
startup
+
V
bulk
I
startup
(eq. 3)
The startup current can be calculated as follows:
I
startup
+ C
Vcc
V
startup
t
startup
) I
CC−start
(eq. 4)
Where:
C
Vcc
Vcc capacitor value
t
startup
Startup time
I
CC−start
IC current consumption (see spec.)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

NCP1215DR2

Mfr. #:
Buy NCP1215DR2
Manufacturer:
ON Semiconductor
Description:
Switching Controllers ANA VARIABL OFF TIME SMPS
Lifecycle:
New from this manufacturer.
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