KAF09000
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4
HORIZONTAL REGISTER
Output Structure
Figure 3. Output Architecture (Left or Right)
Floating
Diffusion
HCCD
Charge
Transfer
Source
Follower
#1
Source
Follower
#2
Source
Follower
#3
RD
RG
OG
H1
H2
VDD
VSS
VOUT
The output consists of a floating diffusion capacitance
connected to a threestage source follower. Charge
presented to the floating diffusion (FD) is converted into a
voltage and is current amplified in order to drive offchip
loads. The resulting voltage change seen at the output is
linearly related to the amount of charge placed on the FD.
Once the signal has been sampled by the system electronics,
the reset gate (RG) is clocked to remove the signal and FD
is reset to the potential applied by reset drain (RD).
Increased signal at the floating diffusion reduces the voltage
seen at the output pin. To activate the output structure, an
offchip current source must be added to the VOUT pin of
the device. See Figure 4.
KAF09000
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5
Output Load
Figure 4. Recommended Output Structure Load Diagram
2N3904
or Equiv.
Buffered
Video
Output
Iout = 5 mA
VDD = +15 V
0.1 μF
VOUT
140 W
1 kW
Note: Component values may be revised based on operating conditions and other design considerations.
KAF09000
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6
PHYSICAL DESCRIPTION
Pin Description and Device Orientation
Figure 5. Pinout Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
LOD
SUB
V2
V2
V1
V1
N/C
N/C
SUB*
SUB*
SUB
OG
VDD
VOUT
VSS
RD
RG
N/C
V2
V2
V1
V1
SUB
N/C
N/C
N/C
SUB*
N/C
N/C
N/C
H2
H1
SUB
Pixel (1,1)
(3056,3056)
N/C
Notes: 1. Pins with the same name are to be tied together on the circuit board and have the same timing.
2. Unlike the KAF16801, pins 9, 10, and, 25 are internally connected to SUB. They may be connected to SUB
on the printed circuit board or may be left floating.
Table 3. PIN DESCRIPTION
Pin Name Description
1 SUB Substrate
2 V2 Vertical CCD Clock Phase 2
3 V2 Vertical CCD Clock Phase 2
4 V1 Vertical CCD Clock Phase 1
5 V1 Vertical CCD Clock Phase 1
6 LOD Anti Blooming Drain
7 N/C No Connection
8 N/C No Connection
9 SUB* No Connection
10 SUB* No Connection
11 SUB Substrate
12 OG Output Gate
13 VDD Output Amplifier Supply
14 VOUT Video Output
15 VSS Output Amplifier Return
16 RD Reset Drain
17 RG Reset Gate
18 SUB Substrate
19 H1 Horizontal Phase 1
20 H2 Horizontal Phase 2
21 N/C No Connection
22 N/C No Connection
23 N/C No Connection
24 N/C No Connection
25 SUB* No Connection
26 N/C No Connection
27 N/C No Connection
28 N/C No Connection
29 N/C No Connection
30 SUB Substrate
31 V1 Vertical CCD Clock Phase 1
32 V1 Vertical CCD Clock Phase 1
33 V2 Vertical CCD Clock Phase 2
34 V2 Vertical CCD Clock Phase 2
*Unlike the KAF16801, pins 9, 10, and, 25 are internally connected
to SUB. They may be connected to SUB on the printed circuit board
or must be left floating.

KAF-09000-ABA-DP-BA

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Image Sensors FULL FRAME CCD IMAGE SENSOR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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