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CS5550-ISZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
CS5550
DS630F1 7
5 V DIGITAL CHARACTERISTICS
3 V DIGITAL CHARACTERISTICS
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Unit
High-Level Input Voltage
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
V
IH
0.6 VD+
(VD+) - 0.5
0.8 VD+
-
-
-
-
-
-
V
V
V
Low-Level Input Voltage
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
V
IL
-
-
-
-
-
-
0.8
1.5
0.2 VD+
V
V
V
High-Level Output Voltage I
out
= +5 mA V
OH
(VD+) - 1.0 - - V
Low-Level Output Voltage I
out
= -5 mA V
OL
--0.4V
Input Leakage Current I
in
-±1±10µA
3-State Leakage Current I
OZ
--±10µA
Digital Output Pin Capacitance C
out
-5-pF
Parameter Symbol Min Typ Max Unit
High-Level Input Voltage
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
V
IH
0.6 VD+
(VD+) - 0.5
0.8 VD+
-
-
-
-
-
-
V
V
V
Low-Level Input Voltage
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
V
IL
-
-
-
-
-
-
0.48
0.3
0.2 VD+
V
V
V
High-Level Output Voltage I
out
= +5 mA V
OH
(VD+) - 1.0 - - V
Low-Level Output Voltage I
out
= -5 mA V
OL
--0.4V
Input Leakage Current I
in
-±1±10µA
3-State Leakage Current I
OZ
--±10µA
Digital Output Pin Capacitance C
out
-5-pF
Parameter Symbol Min Typ Max Unit
Positive Digital Power Supply VD+ 3.135 3.3 5.25 V
Positive Analog Power Supply VA+ 4.75 5 5.25 V
Negative Analog Power Supply AGND -0.25 0 0.25 V
Voltage Reference VREF - 2.5 - V
Specified Temperature Range T
A
-40 - +85 °C
CS5550
8 DS630F1
SWITCHING CHARACTERISTICS
Notes: 7. Device parameters are specified with a 4.096 MHz clock. If a crystal is used, then XIN frequency must
remain between 2.5 MHz - 5.0 MHz.
8. If external MCLK is used, then its duty cycle must be between 45% and 55% to maintain this spec.
9. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.
10. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.
Parameter Symbol Min Typ Max Unit
Master Clock Frequency Internal Gate Oscillator (Note 7) MCLK 2.5 4.096 5 MHz
Master Clock Duty Cycle 40 - 60 %
CPUCLK Duty Cycle (Note 8) 40 60 %
Rise Times Any Digital Input Except SCLK
(Note 9) SCLK
Any Digital Output
t
rise
-
-
-
-
-
50
1.0
100
-
µs
µs
ns
Fall Times Any Digital Input Except SCLK
(Note 9) SCLK
Any Digital Output
t
fall
-
-
-
-
-
50
1.0
100
-
µs
µs
ns
Start-up
Oscillator Start-Up Time XTAL = 4.096 MHz (Note 10) t
ost
-60-ms
Serial Port Timing
Serial Clock Frequency SCLK - - 2 MHz
Serial Clock Pulse Width High
Pulse Width Low
t
1
t
2
200
200
-
-
-
-
ns
ns
SDI Timing
CS
Falling to SCLK Rising t
3
50 - - ns
Data Set-up Time Prior to SCLK Rising t
4
50 - - ns
Data Hold Time After SCLK Rising t
5
100 - - ns
SCLK Falling Prior to CS
Disable t
6
100 - - ns
SDO Timing
CS
Falling to SDI Driving t
7
-2050ns
SCLK Falling to New Data Bit (hold time) t
8
-2050ns
CS
Rising to SDO Hi-Z t
9
-2050ns
CS5550
DS630F1 9
CS
SCLK
MSB MSB - 1
LSB
t
2
t
1
t
3
SDI
MSB MSB - 1
LSB
Command Time 8 SCLKs
LSB
t
6
MSB MSB - 1
LSB
MSB MSB - 1
High Byte Mid Byte Low Byte
t
t
45
SDI Write Timing (Not to Scale)
CS
SDO
SCLK
MSB MSB - 1
LSB
t
2
t
1
t
8
t
7
SDI
MSB MSB - 1
LSB
Command Time 8 SCLKs
LSB
t
9
MSB MSB - 1
LSB
MSB MSB - 1
High Byte Mid Byte
Low Byte
M
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s
t
s
t
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o
b
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S
Y
N
C
0
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D
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SDO Read Timing (Not to Scale)
Figure 1. CS5550 Read and Write Timing Diagrams
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

CS5550-ISZ

Mfr. #:
Buy CS5550-ISZ
Manufacturer:
Cirrus Logic
Description:
Analog to Digital Converters - ADC 2-Ch Low-Cost 24-Bit ADC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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