501MLFT Datasheet 501MLFT, 501MLF, 501MILF | P1-P3

DATASHEET

LOCO™ PLL CLOCK MULTIPLIER ICS501

IDT™ / ICS™

LOCO™ PLL CLOCK MULTIPLIER 1

ICS501 REV S 20170331

Description

The ICS501 LOCO

is the most cost effective way to

generate a high-quality, high-frequency clock output from a

lower frequency crystal or clock input. The name LOCO

stands for Low Cost Oscillator, as it is designed to replace

crystal oscillators in most electronic systems. Using

Phase-Locked Loop (PLL) techniques, the device uses a

standard fundamental mode, inexpensive crystal to

produce output clocks up to 160 MHz.

Stored in the chip’s ROM is the ability to generate nine

different multiplication factors, allowing one chip to output

many common frequencies (see table on page 2).

The device also has an output enable pin which tri-states

the clock output when the OE pin is taken low.

This product is intended for clock generation. It has low

output jitter (variation in the output period), but input to

output skew and jitter are not defined or guaranteed. For

applications which require defined input to output skew, use

the ICS570B.

Features

• Packaged as 8-pin SOIC, MSOP, or die

• RoHS 5 (green) or RoHS 6 (green and lead free)

compliant packaging

• IDT’s lowest cost PLL clock

• Zero ppm multiplication error

• Input crystal frequency of 5 - 27 MHz

• Input clock frequency of 2 - 50 MHz

• Output clock frequencies up to 160 MHz

• Extremely low jitter of 25 ps (one sigma)

• Compatible with all popular CPUs

• Duty cycle of 45/55 up to 160 MHz

• Nine selectable frequencies

• Operating voltage of 3.3 V or 5.0 V

• Tri-state output for board level testing

• 25 mA drive capability at TTL levels

• Ideal for oscillator replacement

• Industrial temperature version available

• Advanced, low-power CMOS process

Block Diagram

CLK

PLL Clock

Multiplier

Circuitry

and ROM

Crystal or

Clock input

GND

VDD

Crystal

Oscillator

S1:0

X1/ICLK

Optional crystal capacitors

ICS501

LOCO™ PLL CLOCK MULTIPLIER CLOCK MULTIPLIER

IDT™ / ICS™

LOCO™ PLL CLOCK MULTIPLIER 2

ICS501 REV S 20170331

Pin Assignment Clock Output Table

0 = connect directly to ground

1 = connect directly to VDD

M = leave unconnected (floating)

Common Output Frequency Examples (MHz)

Pin Descriptions

X1/ICLK

VDD

GND

CLK

X21

8 Pin (150 mil) SOIC

S1 S0 CLK Minimum Input

0 0 4X input per page 5

0 M 5.3125X input 20 MHz

0 1 5X input per page 5

M 0 6.25X input 4 MHz

M M 2X input per page 5

M 1 3.125X input 8 MHz

1 0 6X input per page 5

1 M 3X input per page 5

1 1 8X input per page 5

Output 20 24 30 32 33.33 37.5 40 48 50 60 62.5

Input 10 12 10 16 16.66 12 10 12 16.66 10 20

Selection (S1, S0) M, M M, M 1, M M, M M, M M, 1 0, 0 0, 0 1, M 1, 0 M, 1

Output 64 66.66 72 75 80 83.33 90 100 106.25 120 125

Input 16 16.66 12 12 10 16.66 15 20 20 15 20

Selection (S1, S0) 0, 0 0, 0 1, 0 M, 0 1, 1 0, 1 1, 0 0, 1 0, M 1, 1 M, 0

Number

Name

Type

Pin Description

1 XI/ICLK Input Crystal connection or clock input.

2 VDD Power Connect to +3.3 V or +5 V.

3 GND Power Connect to ground.

4 S1 Tri-level Iinput Select 1 for output clock. Connect to GND or VDD or float.

5 CLK Output Clock output per table above.

6 S0 Tri-level Input Select 0 for output clock. Connect to GND or VDD or float.

7 OE Input Output enable. Tri-states CLK output when low. Internal pull-up.

8 X2 Output Crystal connection. Leave unconnected for clock input.

ICS501

LOCO™ PLL CLOCK MULTIPLIER CLOCK MULTIPLIER

IDT™ / ICS™

LOCO™ PLL CLOCK MULTIPLIER 3

ICS501 REV S 20170331

External Components

Decoupling Capacitor

As with any high-performance mixed-signal IC, the ICS501

must be isolated from system power supply noise to perform

optimally.

A decoupling capacitor of 0.01µF must be connected

between VDD and the GND. It must be connected close to

the ICS501 to minimize lead inductance. No external power

supply filtering is required for the ICS501.

Series Termination Resistor

A 33 terminating resistor can be used next to the CLK pin

for trace lengths over one inch.

Crystal Load Capacitors

The total on-chip capacitance is approximately 12 pF. A

parallel resonant, fundamental mode crystal should be

used. The device crystal connections should include pads

for small capacitors from X1 to ground and from X2 to

ground. These capacitors are used to adjust the stray

capacitance of the board to match the nominally required

crystal load capacitance. Because load capacitance can

only be increased in this trimming process, it is important to

keep stray capacitance to a minimum by using very short

PCB traces (and no vias) between the crystal and device.

Crystal capacitors, if needed, must be connected from each

of the pins X1 and X2 to ground.

The value (in pF) of these crystal caps should equal (C

-12

pF)*2. In this equation, C

= crystal load capacitance in pF.

Example: For a crystal with a 16 pF load capacitance, each

crystal capacitor would be 8 pF [(16-12) x 2 = 8].

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the ICS501. These ratings, which are

standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these

or any other conditions above those indicated in the operational sections of the specifications is not implied.

Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical

parameters are guaranteed only over the recommended operating temperature range.

Recommended Operation Conditions

Item Rating

Supply Voltage, VDD 7 V

All Inputs and Outputs -0.5 V to VDD+0.5 V

Ambient Operating Temperature -40 to +85C

Storage Temperature -65 to +150C

Soldering Temperature 260C

Parameter Min. Typ. Max. Units

Ambient Operating Temperature (commercial) 0 +70 C

Ambient Operating Temperature (industrial) -40 85 C

Power Supply Voltage (measured in respect to GND) +3.0 +5.25 V

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501MLFT

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