Document Number: 70068
S11-1029–Rev. D, 23-May-11
www.vishay.com
5
Vishay Siliconix
DG528, DG529
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
DETAILED DESCRIPTION
The internal structure of the DG528/DG529 includes a 5-V
logic interface with input protection circuitry followed by a
latch, level shifter, decoder and finally the switch constructed
with parallel n- and p-channel MOSFETs (see Figure 1).
The logic interface circuit compares the TTL input signal
against a TTL threshold reference voltage. The output of the
comparator feeds the data input of a D type latch. The level
sensitive D latch continuously places the D
X
input signal on
the Q
X
output when the WR input is low, resulting in transpar-
ent latch operation. As soon as WR returns high, the latches
hold the data last present on the D
X
input, subject to the mini-
mum input timing requirements.
Following the latches the Q
X
signals are level shifted and
decoded to provide proper drive levels for the CMOS
switches. This level shifting insures full on/off switch operation
for any analog signal present between the V+ and V- supply
rails.
The EN pin is used to enable the address latches during the
WR
pulse. It can be hard-wired to the logic supply or to V+ if
one of the channels will always be used (except during a reset)
or it can be tied to address decoding circuitry for memory
mapped operation. The RS
pin is used as a master reset. All
latches are cleared regardless of the state of any other latch
or control line. The WR
pin is used to transfer the state of the
address control lines to their latches, except during a reset or
when EN is low (see Truth Tables).
Figure 1.
V+
V+
V+
Latches
EN
CLK
RESET
A
X
WR
RS
V
REF
D
O
D
n
Q
O
Q
n
Level
Shift
V+
V-
V-
V-
V-
GND
V-
V+
D
V-
V+
Decode
S
1
V-
V+
V-
V+
V+
S
n
Figure 2.
3 V
0
3 V
0
50 %
80 %
80 %
EN
t
W
t
S
t
H
WR
A
0
, A
1
, (A
2
)
Figure 3.
3 V
0
0
50 %
t
RS
t
OFF
(RS)
RS
80 %
V
O
Switch
Output
