MAX158BCAI+T

Interface Mode 0
Figure 5 shows the timing diagram for Mode 0 opera-
tion. This is used with microprocessors that have WAIT
state capability, whereby a READ instruction is extend-
ed to accommodate slow-memory devices. Taking CS
and RD low latches the analog multiplexer address and
starts a conversion. Data outputs DB0–DB7 remain in
the high-impedance condition until the conversion is
complete.
There are two status outputs: Interrupt (INT) and Ready
(RDY). RDY, an open-drain output (no internal pull-up
device), is connected to the processor’s READY/WAIT
input. RDY goes low on the falling edge of CS and goes
high impedance at the end of the conversion, when the
conversion result appears on the data outputs. If the
RDY output is not required, its external pull-up resistor
can be omitted. INT goes low when the conversion is
complete and returns high on the rising edge of CS or
RD.
Interface Mode 1
Mode 1 is designed for applications where the micro-
processor is not forced into a WAIT state. Taking CS
and RD low latches the multiplexer address and starts
a conversion (Figure 6). Data from the previous
conversion is immediately read from the outputs
(DB0–DB7).
INT goes high at the rising edge of CS or RD and goes
low at the end of the conversion. A second READ oper-
ation is required to read the result of this conversion.
The second READ latches a new multiplexer address
and starts another conversion. A delay of 2.5µs must
be allowed between READ operations. RDY goes low
on the falling edge of CS and goes high impedance at
the rising edge of CS. If RDY is not needed, its external
pull-up resistor can be omitted.
MAX154/MAX158
CMOS High-Speed 8-Bit ADCs with
Multiplexer and Reference
_______________________________________________________________________________________ 7
500ns
V
IN
IS TRACKED
BY INTERNAL 
COMPARATORS
V
IN
IS SAMPLED
AND THE FOUR MSBs
ARE LATCHED
SETUP TIME REQUIRED
BY THE INTERNAL
COMPARATORS PRIOR TO
STARTING CONVERSION
600ns
RD
INT GOING LOW INDICATES
THAT CONVERSION IS
COMPLETE AND THAT
DATA CAN BE READ
1000ns
Figure 4. Operating Sequence
DATA
DATA
VALID
ADDR
VALID
ADDR
VALID
INT
RDY
RD
ANALOG
CHANNEL
ADDRESS
CS
t
AS
t
AH
t
RDY
t
CRD
HIGH IMPEDANCE
t
CSS
t
CSS
t
INTH
t
DH
t
ACC2
t
AS
t
P
t
CSH
Figure 5. Mode 0 Timing Diagram
MAX154/MAX158
_____________Analog Considerations
Reference and Input
The V
REF
+ and V
REF
- inputs of the converter define the
zero and the full-scale of the ADC. In other words, the
voltage at V
REF
- is equal to the input voltage that pro-
duces an output code of all zeros, and the voltage at
V
REF
+ is equal to input voltage that produces an output
code of all ones (Figure 7).
Figure 8 shows some possible reference configura-
tions. A 0.01µF bypass capacitor to GND should be
used to reduce the high-frequency output impedance
of the internal reference. Larger capacitors should not
be used, as this degrades the stability of the reference
buffer. The 2.5V reference output is with respect to the
GND pin.
Bypassing
A 47µF electrolytic and 0.1µF ceramic capacitor should
be used to bypass the V
DD
pin to GND. These capaci-
tors must have minimum lead length, since excess lead
length may contribute to conversion errors and insta-
bility. If the reference inputs are driven by long lines,
they should be bypassed to GND with 0.1µF capac-
itors at the reference input pins.
CMOS High-Speed 8-Bit ADCs with
Multiplexer and Reference
8 _______________________________________________________________________________________
DATA
NEW
DATA
ADDR
VALID
INT
RDY
RD
ANALOG
CHANNEL
ADDRESS
CS
t
AS
t
AH
t
RDY
t
ACCI
t
CRD
t
RD
t
CSS
t
RD
t
RDY
t
INTH
t
DH
t
AH
t
INTH
t
AS
t
P
t
CSS
t
CSH
ADDR
VALID
OLD
DATA
t
DH
t
CSH
t
ACCI
Figure 6. Mode 1 Timing Diagram
11111111
11111110
11111101
00000011
00000010
00000001
00000000
1
V
REF
-
23
FS
V
REF
+
FS–1LSB
OUTPUT
CODE
FULL-SCALE
TRANSITION
1LSB = F8 = V
REF
+ - V
REF
-
256 256
AIN INPUT VOLTAGE 
(IN TERMS OF LSBs)
Figure 7. Transfer Function
Input Current
The converters’ analog inputs behave somewhat differ-
ently from conventional ADCs. The sampled data com-
parators take varying amounts of current from the input,
depending on the cycle they are in. The equivalent cir-
cuit of the converter is shown in Figure 9a. When the
conversion starts, AIN(n) is connected to the MS and
LS comparators. Thus, AIN(n) is connected to thirty-one
1pF capacitors.
To acquire the input signal in approximately 1µs, the input
capacitors must charge to the input voltage through the
on-resistance of the multiplexer (about 600) and the
comparator’s analog switches (2kto 5kper compara-
tor). In addition, about 12pF of stray capacitance must be
charged. The input can be modeled as an equivalent RC
network shown in Figure 9b. As R
S
(source impedance)
increases, the capacitors take longer to charge.
Since the length of the input acquisition time is internal-
ly set, large source resistances (greater than 100) will
cause settling errors. The output impedance of an op-
amp is its open-loop output impedance divided by the
loop gain at the frequency of interest. It is important
that the amplifier driving the converter input have suffi-
cient loop gain at approximately 1MHz to maintain low
output impedance.
Input Filtering
The transients in the analog input caused by the sam-
pled data comparators do not degrade the converter’s
performance, since the ADC does not “look” at the
input when these transients occur. The comparator’s
outputs track the input during the first 1µs of the con-
version, and are then latched. Therefore, at least 1µs
will be provided to charge the ADC’s input capaci-
tance. It is not necessary to filter these transients with
an external capacitor on the AIN terminals.
Sinusoidal Inputs
The MAX154/MAX158 can measure input signals with
slew rates as high as 157mV/µs to the rated specifications.
This means that the analog input frequency can be as
high as 10kHz without the aid of an external track/hold.
The maximum sampling rate is limited by the conversion
time (typical t
CRD
= 2µs) plus the time required between
conversions (t
p
= 500ns). It is calculated as:
f
MAX
=
1
=
1
=
400kHz
t
CRD
+ t
p
(2.0 + 0.5) µs
f
MAX
permits a maximum sampling rate of 50kHz per
channel when using the MAX158 and 100kHz per
channel when using the MAX154. These rates are well
above the Nyquist requirement of 20kHz sampling rate
for a 10kHz input bandwidth.
MAX154/MAX158
CMOS High-Speed 8-Bit ADCs with
Multiplexer and Reference
_______________________________________________________________________________________ 9
MAX154
MAX158
V
IN
GND
V
DD
REFOUT
V
REF
+
AIN
x
(+)
AIN
x
(-)
+5V
0.1µF47µF
0.01µF
V
REF
-
MAX154
MAX158
V
IN
GND
V
DD
V
REF
+
AIN
x
(+)
AIN
x
(-)
+5V
0.1µF
47µF
V
REF
-
MAX154
MAX158
V
IN
GND
* Current path must
still exist from
V
IN(-)
to Ground
V
DD
V
REF
+
AIN
x
(+)
AIN
x
(-)
*
+5V
2.5V
0.1µF
47µF
V
REF
-
Figure 8a. Internal Reference
Figure 8b. Power Supply as Reference
Figure 8c. Inputs Not Referenced to GND

MAX158BCAI+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 8-Bit 4Ch 400ksps 5V Precision ADC
Lifecycle:
New from this manufacturer.
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