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8S89833AKILF

P1-P3P4-P6P7-P9P10-P12P13-P15
1©2017 Integrated Device Technology, Inc. September 22, 2017
Description
The 8S89833 is a high speed 1-to-4 Differential-to-LVDS Fanout
Buffer with Internal Termination. The 8S89833 is optimized for high
speed and very low output skew, making it suitable for use in
demanding applications such as SONET, 1 Gigabit and 10 Gigabit
Ethernet, and Fibre Channel. The internally terminated differential
input and V
REF_AC pin allow other differential signal families such as
LVPECL, LVDS, and CML to be easily interfaced to the input with
minimal use of external components. The device also has an output
enable pin which may be useful for system test and debug purposes.
The 8S89833 is packaged in a small 3mm x 3mm 16-pin VFQFN
package which makes it ideal for use in space-constrained
applications.
Features
• Four differential LVDS outputs
• IN, nIN input pair can accept the following differential input levels:
LVPECL, LVDS, CML
• Output frequency: 2GHz
• Cycle-to-cycle jitter, RMS: 3.5ps (maximum)
• Additive phase jitter, RMS: 0.03ps (typical)
• Output skew: 30ps (maximum)
• Part-to-part skew: 200ps (maximum)
• Propagation Delay: 600ps (maximum)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
8S89833
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
Block Diagram
Pin Assignment
50Ω
50Ω
DQ
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
IN
V
T
nIN
V
REF_AC
EN
Pullup
5 6 7 8
16 15 14 13
1
2
3
4
12
11
10
9
Q0
n
Q0
Q1
n
Q1
IN
V
T
V
REF_A
C
nIN
Q2
n
Q2
V
DD
EN
Q3
V
DD
GN
D
nQ
3
8S89833
Datasheet
Low Skew, 1-To-4 Differential-To-LVDS
Fanout Buffer w/Internal Termination
2©2017 Integrated Device Technology, Inc. September 22, 2017
8S89833 Datasheet
Table 1. Pin Descriptions
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 2 Q0, nQ0 Output
Differential output pair. Normally terminated with 100 across the pair. LVDS interface
levels.
3, 4 Q1, nQ1 Output
Differential output pair. Normally terminated with 100 across the pair. LVDS interface
levels.
5, 6 Q2, nQ2 Output
Differential output pair. Normally terminated with 100 across the pair. LVDS interface
levels.
7, 14 V
DD
Power Power supply pins.
8 EN Input Pullup
Synchronizing output enable pin. When LOW, disables outputs. When HIGH, enables
outputs. Internally connected to a 37k
pullup resistor. LVTTL / LVCMOS interface levels.
9 nIN Input Inverting differential LVPECL clock input. RT = 50
termination to V
T
.
10 V
REF_AC
Output
Reference voltage for AC-coupled applications. Equal to V
DD
- 1.4V (approx.). Maximum
sink/source current is ±2mA.
11 V
T
Input
Input termination center-tap. Each side of the differential input pair terminates to a V
T
pin.
The V
T
pins provide a center-tap to a termination network for maximum interface flexibility.
12 IN Input Non-inverting differential clock input. RT = 50
termination to V
T
.
13 GND Power Power supply ground.
15, 16 Q3, nQ3 Output
Differential output pair. Normally terminated with 100 across the pair. LVDS interface
levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
R
PULLUP
Input Pullup Resistor 37 k
3©2017 Integrated Device Technology, Inc. September 22, 2017
8S89833 Datasheet
Function Tables
Table 3. Control Input Function Table
NOTE 1: On the next negative transition of the input signal (IN).
Figure 1. EN Timing Diagram
Inputs Outputs
IN nIN EN Q[0:3] nQ[0:3]
011 0 1
101 1 0
X X 0 Disabled LOW
NOTE 1
Disabled HIGH
NOTE 1
←
→
t
PD
t
S
t
H
V
OD
V
DD
/2V
DD
/2
V
IN
EN
nIN
IN
nQx
Qx
P1-P3P4-P6P7-P9P10-P12P13-P15

8S89833AKILF

Mfr. #:
Buy 8S89833AKILF
Manufacturer:
IDT
Description:
Clock Drivers & Distribution Low Skew,1-to-4 LVDS Fanout Buffer
Lifecycle:
New from this manufacturer.
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