7©2017 Integrated Device Technology, Inc. September 22, 2017
8S89833 Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a Phase
noise plot and is most often the specified plot in many applications.
Phase noise is defined as the ratio of the noise power present in a
1Hz band at a specified offset from the fundamental frequency to the
power value of the fundamental. This ratio is expressed in decibels
(dBm) or a ratio of the power in the 1Hz band to the power in the
fundamental. When the required offset is specified, the phase noise
is called a dBc value, which simply means dBm at a specified offset
from the fundamental. By investigating jitter in the frequency
domain, we get a better understanding of its effects on the desired
application over the entire time record of the signal. It is
mathematically possible to calculate an expected bit error rate given
a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device.
This is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator “IFR2042 10kHz – 6.4GHz Low Noise Signal
Generator as external input to an Agilent 8133A 3GHz Pulse
Generator”.
Additive Phase Jitter @ 622.08MHz
12kHz to 20MHz = 0.03ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
8©2017 Integrated Device Technology, Inc. September 22, 2017
8S89833 Datasheet
Parameter Measurement Information
LVDS Output Load AC Test Circuit
Part-to-Part Skew
Cycle-to-Cycle Jitter, RMS
Differential Input Level
Output Skew
Propagation Delay
V
DD
nQx
Qx
nQy
Qy
tsk(pp)
P
art 1
P
art 2
nQ[0:3]
Q[0:3]
tcycle n tcycle n+1
tjit(cc) =
|
tcycle n – tcycle n+1
|
1000 Cycles
nIN
IN
V
DD
GND
V
IH
Cross Points
V
IN
V
IL
Qx
nQx
Qy
nQy
t
PD
nQ[0:3]
Q[0:3]
nIN
IN
9©2017 Integrated Device Technology, Inc. September 22, 2017
8S89833 Datasheet
Parameter Measurement Information, continued
Single-Ended & Differential Input Voltage Swing
Offset Voltage Setup
Output Rise/Fall Time
Differential Output Voltage Setup
V
IN
V
DIFF_IN
Differential Voltage Swing = 2 x Single-ended V
IN
20%
80%
80%
20%
t
R
t
F
V
OD
nQ[0:3]
Q[0:3]

8S89833AKILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution Low Skew,1-to-4 LVDS Fanout Buffer
Lifecycle:
New from this manufacturer.
Delivery:
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