September 1996
NDT452P
P-Channel Enhancement Mode Field Effect Transistor
General Description Features
____________________________________________________________________________________________________________
Absolute Maximum Ratings T
A
= 25°C unless otherwise noted
Symbol Parameter NDT452P Units
V
DSS
Drain-Source Voltage -30 V
V
GSS
Gate-Source Voltage ±20 V
I
D
Drain Current - Continuous (Note 1a) ±3 A
- Pulsed ±20
P
D
Maximum Power Dissipation (Note 1a) 3 W
(Note 1b) 1.3
(Note 1c)
1.1
T
J
,T
STG
Operating and Storage Temperature Range -65 to 150 °C
THERMAL CHARACTERISTICS
R
θ
JA
Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W
R
θ
JC
Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W
* Order option J23Z for cropped center drain lead.
NDT452P Rev. C3
Power SOT P-Channel enhancement mode power field
effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance and provide superior switching
performance. These devices are particularly suited for low
voltage applications such as notebook computer power
management and DC motor control.
-3A, -30V. R
DS(ON)
= 0.18 @ V
GS
= -10V.
High density cell design for extremely low R
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
D
D S
G
D
S
G
© 1997 Fairchild Semiconductor Corporation
Electrical Characteristics (T
A
= 25°C unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage V
GS
= 0 V, I
D
= -250 µA -30 V
I
DSS
Zero Gate Voltage Drain Current
V
DS
= -24 V, V
GS
= 0 V
-2 µA
T
J
= 55°C
-25 µA
I
GSSF
Gate - Body Leakage, Forward V
GS
= 20 V, V
DS
= 0 V 100 nA
I
GSSR
Gate - Body Leakage, Reverse
V
GS
= -20 V, V
DS
= 0 V
-100 nA
ON CHARACTERISTICS (Note 2)
V
GS(th)
Gate Threshold Voltage V
DS
= V
GS
, I
D
= -250 µA -1 -2 -3 V
T
J
=125°C -0.85 -1.7 -2.6
R
DS(ON)
Static Drain-Source On-Resistance
V
GS
= -10 V, I
D
= -3 A
0.15 0.18
T
J
=125°C
0.23 0.32
V
GS
= -4.5 V, I
D
= - 2.2 A 0.27 0.32
I
D(on)
On-State Drain Current
V
GS
= -10 V, V
DS
= -5 V
-15 A
V
GS
= -4.5 V, V
DS
= -5 V -4.5
g
FS
Forward Transconductance
V
DS
= -15 V, I
D
= -3 A
3.7 S
DYNAMIC CHARACTERISTICS
C
iss
Input Capacitance V
DS
= -10 V, V
GS
= 0 V,
f = 1.0 MHz
525 pF
C
oss
Output Capacitance 300 pF
C
rss
Reverse Transfer Capacitance 130 pF
SWITCHING CHARACTERISTICS (Note 2)
t
D(on)
Turn - On Delay Time
V
DD
= -10 V, I
D
= -1.0 A,
V
GEN
= -10 V, R
GEN
= 6
8 40 ns
t
r
Turn - On Rise Time 15 40 ns
t
D(off)
Turn - Off Delay Time 25 90 ns
t
f
Turn - Off Fall Time 8 50 ns
Q
g
Total Gate Charge
V
DS
= -10 V,
I
D
= -3 A, V
GS
= -10 V
15 25 nC
Q
gs
Gate-Source Charge 1.6 4 nC
Q
gd
Gate-Drain Charge 4.5 8 nC
NDT452P Rev. C3
Electrical Characteristics (T
A
= 25°C unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward Current -2.5 A
V
SD
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= -3 A
(Note 2)
-1.2 V
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
P
D
(
t
)
=
T
J
T
A
R
θJ A
(t)
=
T
J
T
A
R
θJ C
+R
θCA
(
t
)
= I
D
2
(t) × R
DS(ON ) T
J
Typical R
θ
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 42
o
C/W when mounted on a 1 in
2
pad of 2oz copper.
b. 95
o
C/W when mounted on a 0.066 in
2
pad of 2oz copper.
c. 110
o
C/W when mounted on a 0.0123 in
2
pad of 2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDT452P Rev. C3
1a
1b
1c

NDT452P

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
MOSFET DISC BY MFG 2/02
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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