ADF4007BCPZ-RL7 Datasheet ADF4007BCPZ, ADF4007BCPZ-RL7 | P10-P12

Data Sheet ADF4007

Rev. B | Page 9 of 16

THEORY OF OPERATION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 9. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed and SW1 and SW2 are

opened. This ensures that there is no loading of the REF

on power-down.

100kΩ

REF

SW1

SW2

BUFFER

SW3

TO R COUNTER

POWER-DOWN

CONTROL

04537-015

Figure 9. Reference Input Stage

RF INPUT STAGE

The RF input stage is shown in Figure 10. It is followed by a

2-stage limiting amplifier to generate the CML clock levels

needed for the prescaler.

500Ω

1.6V

500Ω

AGND

BIAS

GENERATOR

04537-016

Figure 10. RF Input Stage

PRESCALER P

The prescaler, operating at CML levels, takes the clock from the

RF input stage and divides it down to a manageable frequency

for the PFD. The prescaler can be selected to be either 8, 16, 32,

or 64, and is effectively the N value in the PLL synthesizer. The

terms N and P are used interchangeably in this data sheet. N1

and N2 set the prescaler values. The prescaler value should be

chosen so that the prescaler output frequency is always less than

or equal to 120 MHz, the maximum specified PFD frequency.

Thus, with an RF frequency of 4 GHz, a prescaler value of 64 is

valid, but a value of 32 or less is not valid.

][

REFIN

VCO

Nf ×=

R COUNTER

The R counter is permanently set to 2. It allows the input reference

frequency to be divided down by 2 to produce the reference clock

to the phase frequency detector (PFD).

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

The PFD takes inputs from the R counter and the N counter

(prescaler, P) and produces an output proportional to the phase

and frequency difference between them. Figure 11 is a simplified

schematic. The PFD includes a fixed, 3 ns delay element that

controls the width of the antibacklash pulse. This pulse ensures

that there is no dead zone in the PFD transfer function and

minimizes phase noise and reference spurs.

LOGIC HI

CLR1

CLR2

DOWN

CPGND

R DIVIDER

3ns

DELAY

N DIVIDER

CHARGE

PUMP

04537-017

LOGIC HI

Figure 11. PFD Simplified Schematic and Timing (In Lock)

ADF4007 Data Sheet

Rev. B | Page 10 of 16

MUXOUT

The output multiplexer on the ADF4007 allows the user

to access various internal points on the chip. The state of

MUXOUT is controlled by the M2 and M1 pins. Figure 12

shows the MUXOUT section in block diagram form.

DGND

CONTROL

MUX

R COUNTER OUTPUT

N COUNTER OUTPUT

DGND

MUXOUT

04537-018

Figure 12. MUXOUT Circuit

PFD Polarity

The PFD polarity is set by the state of M2 and M1 pins as given

in the Table 5. The ability to set the polarity allows the use of VCOs

with either positive or negative tuning characteristics. For standard

VCOs with positive characteristics (output frequency increases

with increasing tuning voltage), the polarity should be set to

positive. This is accomplished by tying M2 and M1 to a logic

low state.

CP Output

The CP output state is also controlled by the state of M2 and M1. It

can be set either to active (so that the loop can be locked) or to

three-state (open the loop). The normal state is CP output active.

Data Sheet ADF4007

Rev. B | Page 11 of 16

APPLICATIONS INFORMATION

FIXED HIGH FREQUENCY LOCAL OSCILLATOR

Figure 13 shows the ADF4007 being used with the HMC358MS8G

VCO from Hittite Microwave Corporation to produce a fixed-

frequency LO (local oscillator), which could be used in satellite

or CATV applications. In this case, the desired LO is 6.7 GHz.

The reference input signal is applied to the circuit at FREF

and, in this case, is terminated in 50 Ω. Many systems would

have either a TCXO or an OCXO driving the reference input

without any 50 Ω termination. To bias the REF

pi n at AV

/2,

ac coupling is used. The value of the coupling capacitor used

depends on the input frequency. The equivalent impedance at

the input frequency should be less than 10 Ω. Given that the dc

input impedance at the REF

pin is 100 kΩ, less than 0.1% of

the signal is lost.

The charge pump output of the ADF4007 drives the loop filter.

In calculating the loop filter component values, a number of items

need to be considered. In this example, the loop filter was designed

so that the overall phase margin for the system is 45°.

Other PLL system specifications are as follows:

= 5 mA

= 100 MHz/V

Loop Bandwidth = 300 kHz

PFD

= 106 MHz

N = 64

All these specifications are needed and used with the ADIsimPLL

to derive the loop filter component values shown in Figure 13.

The circuit in Figure 13 gives a typical phase noise performance

of −100 dBc/Hz at 10 kHz offset from the carrier. Spurs are

heavily attenuated by the loop filter and are below −90 dBc.

The loop filter output drives the VCO, which, in turn, is fed

back to the RF input of the PLL synthesizer and also drives the

RF output terminal. A T-circuit configuration provides 50 Ω

matching between the VCO output, the RF output, and the RF

terminal of the synthesizer.

ADF4007

100pF 100pF

100pF

MUXOUT

GND

5.6nF

51Ω

18Ω

22Ω

NOTE

DECOUPLING CAPACITORS (0.1mF/10pF) ONAV

, DV

, AND V

OF THEADF4007 AND ON

OF THEAD820 AND THE HMC358MS8G HAVE BEEN OMITTED FROM THE DIAGRAM

TO AID CLARITY.

SET

FREF

VCO

100MHz/V

HMC358MS8G

SET

5.1kΩ

04537-019

GND

47nF

REF

= 3.3V

1kΩ

18kΩ

= 12V

= 3.3V

1kΩ

AD820

10pF

18Ω

100pF

18Ω

100pF

OUT

LOGIC HI

LOGIC LO

Figure 13. 6.78 GHz Local Oscillator Using the ADF4007

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

ADF4007BCPZ-RL7

Mfr. #:

Buy ADF4007BCPZ-RL7

Manufacturer:

Analog Devices Inc.

Description:

Phase Locked Loops - PLL High Freq Divider/ Synthesizer

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

ADF4007BCPZ-RL7

ADF4007BCPZ-RL7

Products related to this Datasheet