LT4180
10
4180fb
For more information www.linear.com/4180
applicaTions inForMaTion
C
LOAD
=
2.2
R
WIRE
• 2 • f
DITHER
Where C
LOAD
is the minimum load decoupling capacitance,
R
WIRE
is the minimum wiring resistance of one conduc-
tor of the wiring pair, and f
DITHER
is the minimum dither
frequency.
Continuing the example, our CAT5 cable has a maximum
9.38Ω/100m conductor resistance.
Maximum wiring resistance is:
R
WIRE
= 2 • 1000ft • 0.305m/ft • 0.0938Ω/m
R
WIRE
= 57.2Ω
With an oscillator tolerance of ±15%, the minimum
dither frequency is 414.8Hz, so the minimum decoupling
capacitance is:
C
LOAD
=
57.2Ω • 2 • 414.8Hz
= 46.36µF
This is the minimum value. Select a nominal value to ac-
count for all factors which could reduce the nominal, such
as initial tolerance, voltage and temperature coefficients
and aging.
CHOLD Capacitor Selection and Compensation
CHOLD1
A 47nF capacitor will suffice for most applications. A
smaller value might allow faster recovery from a sudden
load change, but care must be taken to ensure full load
p-p ripple at this node is kept within 5mV:
CHOLD2 = CHOLD3 =
f
DITHER
(kHz)
For a dither frequency of 488Hz:
CHOLD2 = CHOLD3 =
0.488(kHz)
= 5.12nF
NPO ceramic or other capacitors with low leakage and di-
electric absorption should be used for all HOLD capacitors.
Set CHOLD4 to 1µF. This value will be adjusted later.
Compensation
Start with a 47pF capacitor between the COMP and DRAIN
pins of the LT4180. Add an RC network in parallel with the
47pF capacitor, 10k and 10nF are good starting values.
Once the output voltage has been confirmed to regulate at
the desired level at no load, increase the load current to the
100% level and monitor the wire current (dither current)
with a current probe. Verify the dither current resembles
a square wave with the desired dither frequency.
If the output voltage is too low, increase the value of the
10k resistor until some overshoot is observed at the leading
edge of the dither current waveform. If the output voltage
is still too low, decrease the value of the 10nF capacitor
and repeat the previous step. Repeat this process until the
full load output voltage increases to within 1% below the
no load level. Refer to Figures 7a, 7b and 7c, which show
compensation of the 12V 1.5A buck regulator Typical Ap-
plication on the data
sheet. Check for proper voltage drop
correction
over the load range. The dither current should
have good half-wave symmetry. Namely, the waveform
should have similar rise and fall times, enough settling time
at top and bottom and minimum to no over/undershoot.
20µs/DIV
V
LOAD
11.2V
I
DITHER
50mA/DIV
4180 F07a
Figure 7a. Dither Current and V
OUT
with
10nF, 10k Compensation 1.5A Load
