a
AD7711A
*
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Charge Balancing ADC
24 Bits No Missing Codes
60.0015% Nonlinearity
2-Channel Programmable Gain Front End
Gains from 1 to 128
Differential Inputs
Low-Pass Filter with Programmable Filter Cutoffs
Ability to Read/Write Calibration Coefficients
Bidirectional Microcontroller Serial Interface
Internal/External Reference Option
Single- or Dual-Supply Operation
Low Power (25 mW typ) with Power-Down Mode
(7 mW typ)
APPLICATIONS
RTD Transducers
LC
2
MOS Signal Conditioning ADC
with RTD Current Source
GENERAL DESCRIPTION
The AD7711A is a complete analog front end for low frequency
measurement applications. The device accepts low level signals
directly from a transducer and outputs a serial digital word. It
employs a sigma-delta conversion technique to realize up to
24 bits of no missing codes performance. The input signal is
applied to a proprietary programmable gain front end based
around an analog modulator. The modulator output is pro-
cessed by an on-chip digital filter. The first notch of this digital
filter can be programmed via the on-chip control register, allow-
ing adjustment of the filter cutoff and settling time.
The part features two differential analog inputs and a differen-
tial reference input. Normally, one of the channels will be used
as the main channel with the second channel used as an auxil-
iary input to periodically measure a second voltage. It can be
operated from a single supply (by tying the V
SS
pin to AGND)
provided that the input signals on the analog inputs are more
positive than –30 mV. By taking the V
SS
pin negative, the part
can convert signals down to –V
REF
on its inputs. The part also
provides a 400 mA current source that can be used to provide
excitation for RTD transducers. The AD7711A thus performs
all signal conditioning and conversion for a single- or dual-
channel system.
The AD7711A is ideal for use in smart, microcontroller based
systems. Input channel selection, gain settings, and signal polar-
ity can be configured in software by using the bidirectional serial
port. The AD7711A contains self-calibration, system calibra-
tion, and background calibration options and allows the user to
read and write the on-chip calibration registers.
*Protected by U.S. Patent No. 5,134,401.
CMOS construction ensures low power dissipation, and a soft-
ware programmable power-down mode reduces the standby
power consumption to only 7 mW typical. The part is available
in a 24-lead, 0.3 inch-wide, hermetic dual-in-line package
(CERDIP), as well as a 24-lead small outline (SOIC) package.
PRODUCT HIGHLIGHTS
1. The programmable gain front end allows the AD7711A
to accept input signals directly from an RTD transducer,
removing a considerable amount of signal conditioning. An
on-chip current source provides the excitation current for
the RTD.
2. The part features excellent static performance specifications
with 24-bit no missing codes, ± 0.0015% accuracy, and low
rms noise (<250 nV). Endpoint errors and the effects of
temperature drift are eliminated by on-chip calibration
options, which remove zero-scale and full-scale errors.
3. The AD7711A is ideal for microcontroller or DSP processor
applications with an on-chip control register that allows
control over filter cutoff, input gain, channel selection, signal
polarity, RTD current control, and calibration modes.
4. The AD7711A allows the user to read and to write the
on-chip calibration registers. This means that the micro-
controller has much greater control over the calibration
procedure.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.
CLOCK
GENERATION
SERIAL INTERFACE
CONTROL
REGISTER
OUTPUT
REGISTER
CHARGE-BALANCING A/D
CONVERTER
AUTO-ZEROED
S-D
MODULATOR
DIGITAL
FILTER
AD7711A
M
U
X
AGND DGND MODE SDATA SCLK A0
MCLK
OUT
MCLK
IN
AIN1(+)
AIN1(–)
REF
IN (–)
REF
IN (+)
SYNC
4.5mA
A = 1 – 128
DRDYTFSRFS
REF OUT
2.5V REFERENCE
AIN2(+)
AIN2(–)
V
SS
V
BIAS
AV
DD
DV
DD
PGA
AV
DD
RTD
CURRENT
400mA
AV
DD
AD7711A* Product Page Quick Links
Last Content Update: 09/06/2016
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Documentation
Application Notes
AN-202: An IC Amplifier User’s Guide to Decoupling,
Grounding, and Making Things Go Right for a Change
AN-283: Sigma-Delta ADCs and DACs
AN-311: How to Reliably Protect CMOS Circuits Against
Power Supply Overvoltaging
AN-388: Using Sigma-Delta Converters-Part 1
AN-389: Using Sigma-Delta Converters-Part 2
AN-397: Electrically Induced Damage to Standard Linear
Integrated Circuits:
AN-406: Using the AD771X Family of 24-Bit Sigma-Delta
A/D Converters
AN-607: Selecting a Low Bandwidth (<15 kSPS) Sigma-
Delta ADC
AN-615: Peak-to-Peak Resolution Versus Effective
Resolution
Data Sheet
AD7711A: LC
2
MOS, Signal Conditioning ADC with RTD
Current Source Data Sheet
Tools and Simulations
Sigma-Delta ADC Tutorial
Reference Materials
Analog Dialogue
Ask the Applications Engineer-27: What problems am I
most likely to run into when instrumenting an industrial
system?
Technical Articles
Delta-Sigma Rocks RF, As ADC Designers Jump On Jitter
MS-2210: Designing Power Supplies for High Speed ADC
Part 1: Circuit Suggestions Using Features and
Functionality of New Sigma-Delta ADCs
Part 2: Circuit Suggestions Using Features and
Functionality of New Sigma-Delta ADCs
Design Resources
AD7711A Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
Discussions
View all AD7711A EngineerZone Discussions
Sample and Buy
Visit the product page to see pricing options
Technical Support
Submit a technical question or find your regional support
number
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.
Parameter A, S Versions
1
Unit Conditions/Comments
STATIC PERFORMANCE
No Missing Codes 24 Bits min Guaranteed by Design. For Filter Notches £ 60 Hz
22 Bits min For Filter Notch = 100 Hz
18 Bits min For Filter Notch = 250 Hz
15 Bits min For Filter Notch = 500 Hz
12 Bits min For Filter Notch = 1 kHz
Output Noise See Tables I and II Depends on Filter Cutoffs and Selected Gain
Integral Nonlinearity @ 25rC ± 0.0015 % FSR max Filter Notches £ 60 Hz
T
MIN
to T
MAX
0.003 % FSR max Typically ± 0.0003%
Positive Full-Scale Error
2, 3, 4
Excluding Reference
Full-Scale Drift
5
1 mV/rC typ Excluding Reference. For Gains of 1, 2
0.3 mV/rC typ Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
Unipolar Offset Error
2, 4
Unipolar Offset Drift
5
0.5 mV/rC typ For Gains of 1, 2
0.25 mV/rC typ For Gains of 4, 8, 16, 32, 64, 128
Bipolar Zero Error
2, 4
Bipolar Zero Drift
5
0.5 mV/rC typ For Gains of 1, 2
0.25 mV/rC typ For Gains of 4, 8, 16, 32, 64, 128
Gain Drift 2 ppm/rC typ
Bipolar Negative Full-Scale Error
2
@ 25rC ± 0.003 % FSR max Excluding Reference
± 0.006 % FSR max Typically ± 0.0006%
Bipolar Negative Full-Scale Drift
5
1 mV/rC typ Excluding Reference. For Gains of 1, 2
T
MIN
to T
MAX
0.3 mV/rC typ Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
ANALOG INPUTS/REFERENCE INPUTS
Common-Mode Rejection (CMR) 100 dB min At dc and AV
DD
= 5 V
90 dB min At dc and AV
DD
= 10 V
Common-Mode Voltage Range
6
V
SS
to AV
DD
V min to V max
Normal-Mode 50 Hz Rejection
7
100 dB min For Filter Notches of 10, 25, 50 Hz, ± 0.02 ¥ f
NOTCH
Normal-Mode 60 Hz Rejection
7
100 dB min For Filter Notches of 10, 30, 60 Hz, ± 0.02 ¥ f
NOTCH
Common-Mode 50 Hz Rejection
7
150 dB min For Filter Notches of 10, 25, 50 Hz, ± 0.02 ¥ f
NOTCH
Common-Mode 60 Hz Rejection
7
150 dB min For Filter Notches of 10, 30, 60 Hz, ± 0.02 ¥ f
NOTCH
DC Input Leakage Current
7
@ 25rC 10 pA max
T
MIN
to T
MAX
1 nA max
Sampling Capacitance
7
20 pF max
Analog Inputs
8
Input Voltage Range
9
For Normal Operation. Depends on Gain Selected
0 to +V
REF
10
nom Unipolar Input Range (B/U Bit of Control Register = 1)
± V
REF
nom Bipolar Input Range (B/U Bit of Control Register = 0)
Input Sampling Rate, f
S
See Table III
Reference Inputs
REF IN(+) REF IN(–) Voltage
11
2.5 to 5 V min to V max For Specified Performance. Part Functions with
Lower V
REF
Voltages
Input Sampling Rate, f
S
f
CLK IN
/256
REFERENCE OUTPUT
Output Voltage 2.5 V nom
Initial Tolerance @ 25rC ± 1 % max
Drift 20 ppm/rC typ
Output Noise 30 mV typ pk-pk Noise 0.1 Hz to 10 Hz Bandwidth
Line Regulation (AV
DD
) 1 mV/V max
Load Regulation 1.5 mV/mA max Maximum Load Current 1 mA
External Current 1 mA max
NOTES
1
Temperature ranges are as follows: A Version, –40rC to +85rC; S Version, –55rC to +125rC.
2
Applies after calibration at the temperature of interest.
3
Positive full-scale error applies to both unipolar and bipolar input ranges.
4
These errors will be of the order of the output noise of the part as shown in Table I when using system calibration. These errors are 20 mV typical when using self-
calibration or background calibration.
5
Recalibration at any temperature or use of the background calibration mode will remove these drift errors.
6
This common-mode voltage range is allowed, provided that the input voltage on AIN(+) and AIN(–) does not exceed AV
DD
+ 30 mV and V
SS
30 mV.
7
These numbers are guaranteed by design and/or characterization.
8
The analog inputs present a very high impedance dynamic load that varies with clock frequency and input sample rate. The maximum recommended source
resistance depends on the selected gain (see Tables IV and V).
9
The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2(–) inputs. The absolute
voltage on the analog inputs should not go more positive than AV
DD
+ 30 mV or go more negative than V
SS
30 mV.
10
V
REF
= REF IN(+) – REF IN(–).
11
The reference input voltage range may be restricted by the input voltage range requirement on the V
BIAS
input.
(AV
DD
= +5 V 6 5%; DV
DD
= +5 V 6 5%; V
SS
= 0 V or 5 V 6 5%; REF IN(+) = +2.5 V;
REF IN() = AGND; MCLK IN = 10 MHz, unless otherwise stated. All specifications T
MIN
to T
MAX
, unless otherwise noted.)
2 REV. D
AD7711ASPECIFICATIONS

AD7711AARZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC CMOS 24B w/ Matched RTD Excitation Crnt
Lifecycle:
New from this manufacturer.
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