AD7711AARZ Datasheet AD7711AARZ, AD7711ASQ, AD7711AAR | P19-P21

REV. D

AD7711A

–18–

System Offset Calibration

System offset calibration is a variation of both the system cali-

bration and self-calibration. In this case, the zero-scale point

for the system is presented to the AIN input of the converter.

System-offset calibration is initiated by writing 1, 0, 0 to MD2,

MD1, MD0. The system zero-scale coefficient is determined by

converting the voltage applied to the AIN input, while the full-

scale coefficient is determined from the span between this AIN

conversion and a conversion on V

REF

. The zero-scale point

should be applied to the AIN input for the duration of the cali-

bration sequence. This is a one-step calibration sequence with

DRDY going low when the sequence is completed. In the uni-

polar mode, the system offset calibration is performed between

the two endpoints of the transfer function; in the bipolar mode,

it is performed between midscale and positive full scale.

Background Calibration

The AD7711A also offers a background calibration mode where

the part interleaves its calibration procedure with its normal

conversion sequence. In the background calibration mode, the

same voltages used as the calibration points in the self-calibra-

tion mode are used, i.e., shorted inputs and V

REF

. The back-

ground calibration mode is invoked by writing 1, 0, 1 to MD2,

MD1, MD0 of the control register. When invoked, the back-

ground calibration mode reduces the output data rate of the

AD7711A by a factor of 6 while the –3 dB bandwidth remains

unchanged. Its advantage is that the part is continually perform-

ing calibration and automatically updating its calibration coeffi-

cients. As a result, the effects of temperature drift, supply

sensitivity, and time drift on zero-scale and full-scale errors are

automatically removed. When the background calibration mode

is turned on, the part will remain in this mode until bits MD2,

MD1, and MD0 of the control register are changed. With back-

ground calibration mode on, the first result from the AD7711A

will be incorrect as the full-scale calibration will not have been

performed. For a step change on the input, the second output

update will have settled to 100% of the final value.

Table VI summarizes the calibration modes and the calibration

points associated with them. It also gives the duration from

when the calibration is invoked to when valid data is available to

the user.

Span and Offset Limits

Whenever a system calibration mode is used, there are limits on

the amount of offset and span that can be accommodated. The

range of input span in both the unipolar and bipolar modes has

a minimum value of 0.8 ¥ V

REF

/GAIN and a maximum value of

2.1 ¥ V

REF

/GAIN.

The amount of offset that can be accommodated depends on

whether the unipolar or bipolar mode is being used. This offset

range is limited by the requirement that the positive full-scale

calibration limit is £ 1.05 ¥ V

REF

/GAIN. Therefore, the offset

range plus the span range cannot exceed 1.05 ¥ V

REF

/GAIN. If

the span is at its minimum (0.8 ¥ V

REF

/GAIN), the maximum

the offset can be is (0.25 ¥ V

REF

/GAIN).

Self-Calibration

In the self-calibration mode with a unipolar input range, the

zero-scale point used in determining the calibration coefficients

is with both inputs shorted (i.e., AIN(+) = AIN(–) = V

BIAS

) and

the full-scale point is V

REF

. The zero-scale coefficient is deter-

mined by converting an internal shorted inputs node. The

full-scale coefficient is determined by the span between this

shorted inputs conversion and a conversion on an internal V

REF

node. The self-calibration mode is invoked by writing the appro-

priate values (0, 0, 1) to the MD2, MD1, and MD0 bits of the

control register. In this calibration mode, the shorted inputs

node is switched in to the modulator first and a conversion is

performed; the V

REF

node is then switched in and another con-

version is performed. When the calibration sequence is com-

plete, the calibration coefficients updated and the filter resettled

to the analog input voltage, the DRDY output goes low. The

self-calibration procedure takes into account the selected gain

on the PGA.

For bipolar input ranges in the self-calibrating mode, the

sequence is very similar to that just outlined. In this case, the

two points that the AD7711A calibrates are midscale (bipolar

zero) and positive full scale.

System Calibration

System calibration allows the AD7711A to compensate for

system gain and offset errors as well as its own internal errors.

System calibration performs the same slope factor calculations

as self-calibration but uses voltage values presented by the sys-

tem to the AIN inputs for the zero-scale and full-scale points.

System calibration is a two-step process. The zero-scale point

must be presented to the converter first. It must be applied to

the converter before the calibration step is initiated and remain

stable until the step is complete. System calibration is initiated

by writing the appropriate values (0, 1, 0) to the MD2, MD1,

and MD0 bits of the control register. The DRDY output from

the device will signal when the step is complete by going low.

After the zero-scale point is calibrated, the full-scale point is

applied, and the second step of the calibration process is initi-

ated by again writing the appropriate values (0, 1, 1) to MD2,

MD1, and MD0. Again the full-scale voltage must be set up

before the calibration is initiated, and it must remain stable

throughout the calibration step. DRDY goes low at the end of

this second step to indicate that the system calibration is com-

plete. In the unipolar mode, the system calibration is performed

between the two endpoints of the transfer function; in the bipolar

mode, it is performed between midscale and positive full scale.

This two-step system calibration mode offers another feature.

After the sequence has been completed, additional offset or gain

calibrations can be performed by themselves to adjust the zero

reference point or the system gain. This is achieved by perform-

ing the first step of the system calibration sequence (by writing

0, 1, 0 to MD2, MD1, MD0). This will adjust the zero-scale or

offset point but will not change the slope factor from what was

set during a full system calibration sequence.

System calibration can also be used to remove any errors from

an antialiasing filter on the analog input. A simple R, C anti-

aliasing filter on the front end may introduce a gain error on the

analog input voltage but the system calibration can be used to

remove this error.

AD7711A

–19–REV. D

In the bipolar mode, the system offset calibration range is again

restricted by the span range. The span range of the converter in

bipolar mode is equidistant around the voltage used for the zero-

scale point, thus the offset range plus half the span range cannot

exceed (1.05 ¥ V

REF

/GAIN). If the span is set to 2 ¥ V

REF

/GAIN,

the offset span cannot move more than ± (0.05 ¥ V

REF

/GAIN)

before the endpoints of the transfer function exceed the input

overrange limits ± (1.05 ¥ V

REF

/GAIN). If the span range is set

to the minimum ± (0.4 ¥ V

REF

/GAIN), the maximum

allowable

offset range is ± (0.65

¥ V

REF

/GAIN).

POWER-UP AND CALIBRATION

On power-up, the AD7711A performs an internal reset, which

sets the contents of the control register to a known state. How-

ever, to ensure correct calibration for the device, a calibration

routine should be performed after power-up.

The power dissipation and temperature drift of the AD7711A

are low and no warm-up time is required before the initial cali-

bration is performed. However, if an external reference is being

used, this reference must have stabilized before calibration is

initiated.

Drift Considerations

The AD7711A uses chopper stabilization techniques to mini-

mize input offset drift. Charge injection in the analog switches

and dc leakage currents at the sampling node are the primary

sources of offset voltage drift in the converter. The dc input

leakage current is essentially independent of the selected gain.

Gain drift within the converter depends primarily upon the

temperature tracking of the internal capacitors. It is not affected

by leakage currents.

Measurement errors due to offset drift or gain drift can be elimi-

nated at any time by recalibrating the converter or by operating

the part in the background calibration mode. Using the system

calibration mode can also minimize offset and gain errors in the

signal conditioning circuitry. Integral and differential linearity

errors are not significantly affected by temperature changes.

POWER SUPPLIES AND GROUNDING

Since the analog inputs and reference input are differential,

most of the voltages in the analog modulator are common-mode

voltages. V

BIAS

provides the return path for most of the analog

currents flowing in the analog modulator. As a result, the V

BIAS

input should be driven from a low impedance to minimize errors

due to charging/discharging impedances on this line. When the

internal reference is used as the reference source for the part,

AGND is the ground return for this reference voltage.

Table VI. Calibration Truth Table

Cal Type MD2, MD1, MD0 Zero-Scale Cal Full-Scale Cal Sequence Duration

Self-Cal 0, 0, 1 Shorted Inputs V

REF

One-Step 9 ¥ 1/Output Rate

System Cal 0, 1, 0 AIN – Two-Step 4 ¥ 1/Output Rate

System Cal 0, 1, 1 – AIN Two-Step 4 ¥ 1/Output Rate

System Offset Cal 1, 0, 0 AIN V

REF

One-Step 9 ¥ 1/Output Rate

Background Cal 1, 0, 1 Shorted Inputs V

REF

One-Step 6 ¥ 1/Output Rate

The analog and digital supplies to the AD7711A are indepen-

dent and separately pinned out to minimize coupling between

the analog and digital sections of the device. The digital filter

will provide rejection of broadband noise on the power supplies,

except at integer multiples of the modulator sampling frequency.

The digital supply (DV

) must not exceed the analog positive

supply (AV

) by more than 0.3 V in normal operation. If sepa-

rate analog and digital supplies are used, the decoupling scheme

shown in Figure 9 is recommended. In systems where AV

5 V and DV

= 5 V, it is recommended that AV

and DV

are driven from the same 5 V supply, although each supply

should be decoupled separately as shown in Figure 9. It is pref-

erable that the common supply is the system’s analog 5 V supply.

It is also important that power is applied to the AD7711A before

signals at REF IN, AIN, or the logic input pins in order to avoid

excessive current. If separate supplies are used for the AD7711A

and the system digital circuitry, then the AD7711A should be

powered up first. If it is not possible to guarantee this, then

current limiting resistors should be placed in series with the

logic inputs.

AD7711A

0.1mF10mF

ANALOG

SUPPLY

0.1mF

DIGITAL +5V

SUPPLY

Figure 9. Recommended Decoupling Scheme

REV. D

AD7711A

–20–

DIGITAL INTERFACE

The AD7711A’s serial communications port provides a flexible

arrangement to allow easy interfacing to industry-standard

microprocessors, microcontrollers, and digital signal processors.

A serial read to the AD7711A can access data from the output

write to the AD7711A can write data to the control register or

the calibration registers.

Two different modes of operation are available, optimized for

different types of interfaces where the AD7711A can act either

as master in the system (it provides the serial clock) or as slave

(an external serial clock can be provided to the AD7711A).

These two modes, labeled self-clocking mode and external clock-

ing mode, are discussed in detail in the following sections.

Self-Clocking Mode

The AD7711A is configured for its self-clocking mode by tying

the MODE pin high. In this mode, the AD7711A provides the

serial clock signal used for the transfer of data to and from the

AD7711A. This self-clocking mode can be used with processors

that allow an external device to clock their serial port, including

most digital signal processors and microcontrollers such as the

68HC11 and 68HC05. It also allows easy interfacing to serial

parallel conversion circuits in systems with parallel data commu-

nication, allowing interfacing to 74XX299 universal shift regis-

ters without any additional decoding. In the case of shift registers,

the serial clock line should have a pull-down resistor instead of

the pull-up resistor shown in Figure 10 and Figure 11.

Read Operation

Data can be read from the output register, the control register,

or the calibration registers. A0 determines whether the data read

accesses data from the control register or from the output/cali-

bration registers. This A0 signal must remain valid for the dura-

tion of the serial read operation. With A0 high, data is accessed

from either the output register or from the calibration registers.

With A0 low, data is accessed from the control register.

The function of the DRDY line is dependent on only the output

update rate of the device and the reading of the output data

the output data register. It is reset high when the last bit of data

(either 16th bit or 24th bit) is read from the output register. If

data is not read from the output register, the DRDY line will

remain low. The output register will continue to be updated at

the output update rate, but DRDY will not indicate this. A read

from the device in this circumstance will access the most recent

word in the output register. If a new data-word becomes avail-

able to the output register while data is being read from the

output register, DRDY will not indicate this and the new data-

word will be lost to the user. DRDY is not affected by reading

from the control register or the calibration registers.

Data can be accessed from the output data register only when

DRDY is low. If RFS goes low with DRDY high, no data trans-

fer will take place. DRDY does not have any effect on reading

data from the control register or from the calibration registers.

Figure 10 shows a timing diagram for reading from the AD7711A

in the self-clocking mode. This read operation shows a read

from the AD7711A’s output data register. A read from the

control register or calibration registers is similar but, in these

cases, the DRDY line is not related to the read function.

Depending on the output update rate, it can go low at any stage

in the control/calibration register read cycle without affecting

the read and its status should be ignored. A read operation from

either the control or calibration register must always read 24 bits

of data from the respective register.

Figure 10 shows a read operation from the AD7711A. For the

timing diagram shown, it is assumed that there is a pull-up

resistor on the SCLK output. With DRDY low, the RFS input

is brought low. RFS going low enables the serial clock of the

AD7711A and also places the MSB of the word on the serial

data line. All subsequent data bits are clocked out on a high to

low transition of the serial clock and are valid prior to the fol-

lowing rising edge of this clock. The final active falling edge

of SCLK clocks out the LSB, and this LSB is valid prior to

the final active rising edge of SCLK. Coincident with the next

falling edge of SCLK, DRDY is reset high. DRDY going high

turns off the SCLK and the SDATA outputs, which means that

the data hold time for the LSB is slightly shorter than for all

other bits.

MSB LSB

THREE-STATE

SDATA (O)

SCLK (O)

RFS (I)

A0 (I)

DRDY (O)

Figure 10. Self-Clocking Mode, Output Data Read Operation

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AD7711AARZ

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Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC CMOS 24B w/ Matched RTD Excitation Crnt

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AD7711AARZ

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