REVISION 8 3/16/16 13 ©2016 INTEGRATED DEVICE TECHNOLOGY, INC.
MPC9772 DATA SHEET
Figure 12. Single versus Dual Transmission Lines
The waveform plots in Figure 13 show the simulation
results of an output driving a single line versus two lines. In
both cases the drive capability of the MPC9772 output buffer
is more than sufficient to drive 50 transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43 ps exists between the two
differently loaded outputs. This suggests the dual line driving
need not be used exclusively to maintain the tight
output-to-output skew of the MPC9772. The output waveform
in Figure 13 shows a step in the waveform, this step is
caused by the impedance mismatch seen looking into the
driver. The parallel combination of the 36 series resistor
plus the output impedance does not match the parallel
combination of the line impedances. The voltage wave
launched down the two lines will equal:
V
L
=V
S
(Z
0
(R
S
+R
0
+Z
0
))
Z
0
=50 || 50
R
S
=36 || 36
R
0
=14
V
L
= 3.0 (25 (18+17+25)
=1.31 V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
Figure 13. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 14 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
Figure 14. Optimized Dual Line Termination
Figure 15. CCLK MPC9772 AC Test Reference
14
In
MPC9772
Output
Buffer
R
S
= 36
Z
O
= 50
OutA
14
In
MPC9772
Output
Buffer
R
S
= 36
Z
O
= 50
OutB0
R
S
= 36
Z
O
= 50
OutB1
Time (ns)
Voltage (V)
3.0
2.5
2.0
1.5
1.0
0.5
0
2 4 6 8 10 12 14
OutB
t
D
= 3.9386
OutA
t
D
= 3.8956
In
14
MPC9772
Output
Buffer
R
S
= 22
Z
O
= 50
R
S
= 22
Z
O
= 50
14 + 22 || 22 = 50 || 50
25 = 25
Pulse
Generator
Z = 50
R
T
= 50
Z
O
= 50
R
T
= 50
Z
O
= 50
MPC9772 DUT
V
TT
V
TT
REVISION 8 3/16/16 14 ©2016 Integrated Device Technology, Inc.
MPC9772 DATA SHEET
Figure 16. Output-to-Output Skew t
SK(O)
Figure 17. Propagation Delay (t
()
, Static Phase
Offset) Test Reference
Figure 18. Output Duty Cycle (DC)
The pin-to-pin skew is defined as the worst case difference in
propagation delay between any similar delay path within a single
device
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
V
CC
V
CC
2
GND
V
CC
V
CC
2
GND
t
SK(O)
V
CC
V
CC
2
GND
t
P
T
0
DC = t
P
/T
0
x 100%
V
CC
V
CC
2
GND
V
CC
V
CC
2
GND
t
()
CCLKx
FB_IN
T
JIT()
= |T
0
-T
1
mean|
CCLKx
FB_IN
The deviation in t
0
for a controlled edge with respect to a t
0
mean in a
random sample of cycles
Figure 19. I/O Jitter
T
N
T
JIT(CC)
= |T
N
-T
N+1
|
T
N+1
T
JIT(PER)
= |T
N
-1/f
0
|
T
0
Figure 20. Cycle-to-Cycle Jitter Figure 21. Period Jitter
The variation in cycle time of a signal between adjacent cycles, over a
random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over a
random sample of cycles
t
F
t
R
V
CC
=3.3 V
2.4
0.55
Figure 22. Output Transition Time Test Reference
NOTES:
1.
2.
3.
4.
5.
6.
7.
CONTROLLING DIMENSIONS: MILLIMETER.
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
DATUMS -L-, -M- AND -N- TO BE DETERMINED
AT DATUM PLANE -H-.
DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE -T-.
DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE -H-.
DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46
(0.018). MINIMUM SPACE BETWEEN
PROTRUSION AND ADJACENT LEAD OR
PROTRUSTION 0.07 (0.003).
F
SECTION AB-AB
ROTATED 90˚ CLOCKWISE
S
L-M
M
0.13 (0.005) N
S
T
PLATING
BASE METAL
D
J
U
S
0.05 (0.002)
0.25 (0.010)
GAGE PLANE
C2
C1
W
K
E
Z
θ1
θ
VIEW AA
2X R
R1
1
13
14 26
27
39
4052
4X 13 TIPS
4X
N0.20 (0.008) H L-M N0.20 (0.008) T L-M
B V
B1
A
S
V1
A1
S1
-L-
-N-
-M-
3X
VIEW Y
VIEW AA
SEATING
PLANE
C
0.10 (0.004) T
4X
θ3
4X
θ2
-H-
-T-
DIM
A
A1
B
B1
C
C1
C2
D
E
F
G
J
K
R1
S
S1
U
V
V1
W
Z
θ1
θ
θ3
θ2
MIN
---
0.05
1.30
0.20
0.45
0.22
0.07
0.08
0.09
MIN
---
0.002
0.051
0.008
0.009
0.018
0.003
0.003
0.004
MAX
1.70
0.20
1.50
0.40
0.35
0.75
0.20
0.20
0.16
---
MAX
0.067
0.008
0.059
0.016
0.030
0.014
0.008
0.008
0.006
---
MILLIMETERS
10.00 BSC
5.00 BSC
10.00 BSC
5.00 BSC
0.65 BSC
0.50 REF
12.00 BSC
6.00 BSC
12.00 BSC
6.00 BSC
0.20 REF
1.00 REF
12˚ REF
12˚ REF
INCHES
0.394 BSC
0.197 BSC
0.394 BSC
0.197 BSC
0.026 BSC
0.020 REF
0.472 BSC
0.236 BSC
0.472 BSC
0.236 BSC
0.008 REF
0.039 REF
12˚ REF
12˚ REF
AB
AB
VIEW Y
C
L
-X-
X=L, M, N
G
CASE 848D-03
ISSUE D
52-LEAD LQFP PACKAGE
REVISION 8 3/16/16 15 ©2016 Integrated Device Technology, Inc.
MPC9772 DATA SHEET 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR

MPC9772AE

Mfr. #:
Manufacturer:
Description:
Clock Generators & Support Products FSL 1-12 LVCMOS PLL Clock Generator, xta
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet