74HC4002PW-Q100,11

74HC_HCT4002_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 18 July 2012 6 of 14
NXP Semiconductors
74HC4002-Q100; 74HCT4002-Q100
Dual 4-input NOR gate
10. Dynamic characteristics
[1] t
pd
is the same as t
PHL
and t
PLH
.
[2] t
t
is the same as t
THL
and t
TLH
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in W):
P
D
=C
PD
V
CC
2
f
i
N+ (C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of outputs.
Table 7. Dynamic characteristics
GND = 0 V; C
L
= 50 pF; for load circuit see Figure 8.
Symbol Parameter Conditions 25 C 40 C to +125 C Unit
Min Typ Max Max
(85 C)
Max
(125 C)
74HC4002-Q100
t
pd
propagation delay nA, nB, nC or nD to nY;
see Figure 7
[1]
V
CC
= 2.0 V - 30 100 125 150 ns
V
CC
= 4.5 V - 11 20 25 30 ns
V
CC
= 6.0 V - 9 17 21 26 ns
V
CC
=5.0V; C
L
=15pF - 9 - - - ns
t
t
transition time see Figure 7
[2]
V
CC
= 2.0 V - 19 75 95 110 ns
V
CC
= 4.5 V - 7 15 19 22 ns
V
CC
= 6.0 V - 6 13 16 19 ns
C
PD
power dissipation
capacitance
per package; V
I
=GNDtoV
CC
[3]
-16- - -pF
74HCT4002-Q100
t
pd
propagation delay nA, nB, nC or nD to nY;
see Figure 7
[1]
V
CC
= 4.5 V - 13 22 28 33 ns
V
CC
= 5.0 V; C
L
=15pF - 11 - - - ns
t
t
transition time V
CC
= 4.5 V; see Figure 7
[2]
- 7 15 19 22 ns
C
PD
power dissipation
capacitance
per package;
V
I
=GNDtoV
CC
1.5 V
[3]
-22- - -pF
74HC_HCT4002_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 18 July 2012 7 of 14
NXP Semiconductors
74HC4002-Q100; 74HCT4002-Q100
Dual 4-input NOR gate
11. Waveforms
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 7. Waveforms showing the input (nA, nB, nC, nD) to output (nY) propagation delays and the output
transition times
Q$
Q%Q&
Q'
LQSXW
Q<
RXWSXW
9
0
9
;
9
,
W
7+/
W
7/+
9
2+
9
0
9
<
9
2/
*1'
DDD
W
3+/
W
3/+
Table 8. Measurement points
Type Input Output
V
M
V
M
V
X
V
Y
74HC4002-Q100 0.5V
CC
0.5V
CC
0.1V
CC
0.9V
CC
74HCT4002-Q100 1.3 V 1.3 V 0.1V
CC
0.9V
CC
Test data is given in Table 9.
Definitions test circuit:
R
T
= termination resistance should be equal to output impedance Z
o
of the pulse generator.
C
L
= load capacitance including jig and probe capacitance.
Fig 8. Test circuit for measuring switching times
001aah768
t
W
t
W
t
r
t
r
t
f
V
M
V
I
negative
pulse
GND
V
I
positive
pulse
GND
10 %
90 %
90 %
10 %
V
M
V
M
V
M
t
f
V
CC
DUT
R
T
V
I
V
O
C
L
G
74HC_HCT4002_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 18 July 2012 8 of 14
NXP Semiconductors
74HC4002-Q100; 74HCT4002-Q100
Dual 4-input NOR gate
Table 9. Test data
Type Input Load Test
V
I
t
r
, t
f
C
L
74HC4002-Q100 V
CC
6.0 ns 15 pF, 50 pF t
PLH
, t
PHL
74HCT4002-Q100 3.0 V 6.0 ns 15 pF, 50 pF t
PLH
, t
PHL

74HC4002PW-Q100,11

Mfr. #:
Manufacturer:
Nexperia
Description:
Logic Gates 74HC4002PW-Q100/TSSOP14/REEL 1
Lifecycle:
New from this manufacturer.
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