Document #: 001-48923 Rev. *C Page 7 of 10
Application Information
Power Supply Filtering Techniques
As in any high speed analog circuitry, noise at the power supply
pins degrades performance. To achieve optimum jitter perfor-
mance, use good power supply isolation practices. Figure 6.
shows a typical filtering scheme. Since all of the current flows
through pin 1, the resistance and inductance between this pin
and the supply is minimized. A 0.01 or 0.1 µF ceramic chip
capacitor is also located close to this pin to provide a short and
low impedance AC path to ground. A 1 to 10 µF ceramic or
tantalum capacitor shouldbe located in the vicinity of this device,
and may be shared with other devices.
Figure 6. Power Supply Filtering
Termination for LVPECL Output
The CY2XP41 implements its LVPECL driver with a current
steering design. For proper operation, it requires resistor termi-
nation. This datasheet specifies a termination voltage of
VDD–2.1 V. Impedance matching is advised for best signal
integrity. Figure 2 on page 6 shows a termination scheme that is
recommended as a guideline. Other suitable clock layouts exist
and it is recommended that the board designers simulate to
guarantee compatibility across all printed circuit and process
variations. The recommended termination is a 40
Ω load, which
is used to achieve the specified common mode and
peak-to-peak voltage swing. For optimal signal integrity, traces
should also be 40
Ω. The device will also operate with 50Ω termi-
nation, but is not specified with such a load.
Crystal Interface
The CY2XP41 is characterized with 10 pF parallel resonant
crystals. The capacitor values shown in Figure 7. are determined
using a 25 MHz 10 pF parallel resonant crystal and are chosen
to minimize the ppm error. Cypress recommends the following
C1 and C2 values: C1 = C2 = 6.8 pF.
Figure 7. Crystal Input Interface
3.3V
10µ
F
0.1μF
V
DD
V
DD
0.01 µF
(Pin 1)
(Pin 8)
XIN
XOUT
External
Crystal
C1
C2
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