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843002AG-01LF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
FemtoClock
®
Crystal-to-3.3V LVPECL
Frequency Synthesizer
843002-01 DATA SHEET
10 REVISION B 4/6/15
LAYOUT GUIDELINE
Figure 4A shows a schematic example of the 843002-01. An
example of LVEPCL termination is shown in this schematic.
Additional LVPECL termination approaches are shown in the
LVPECL Termination Application Note. In this example, an 18
FIGURE 4A. 843002-01 SCHEMATIC EXAMPLE
pF parallel resonant 26.5625MHz crystal is used. The C1=27pF
and C2=33pF are recommended for frequency accuracy. For
different board layout, the C1 and C2 may be slightly adjusted
for optimizing frequency accuracy.
PC BOARD LAYOUT EXAMPLE
Figure 4B shows an example of 843002-01 P.C. board layout.
The crystal X1 footprint shown in this example allows installation
of either surface mount HC49S or through-hole HC49 package.
The footprints of other components in this example are listed in
the Table 6. There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that
the board has clean analog power ground plane.
FIGURE 4B. 843002-01 PC BOARD LAYOUT EXAMPLE
C1
27pF
VCC
VCCO
Zo = 50 Ohm
R6
50
C6
0.1u
C4
0.01u
VCC
X1
25 MHz
VCC=3.3V
18pF
To Logic
Input
pins
C7
0.1u
Zo = 50 Ohm
RU1
1K
To Logic
Input
pins
C9
0.1u
Set Logic
Input to
'1'
V CCO=3.3V
VCC
VCC
R5
50
U1
ICS843002-01
2
3
4
5
6
7
8
9
1011
12
13
14
15
16
17
18
19
20 1
VCCO
Q0
nQ0
MR
nPLL_SEL
nc
VCCA
F_SEL0
VCCF_SEL1
XTAL_OUT
XTAL_IN
TEST_CLK
nXTAL_SEL
VCC
VEE
nQ1
Q1
VCCO nc
VCC
VCCO
RD2
1K
VCCA
R4
50
C3
10uF
Zo = 50 Ohm
RD1
Not Install
R2
10
Set Logic
Input to
'0'
Zo = 50 Ohm
+
-
C8
0.1u
R7
50
Logic Control Input Examples
R9
50
C2
33pF
R8
50
+
-
RU2
Not Install
Reference Size
C1, C2 0402
C3
0805
C4, C5, C6, C7, C8
0603
R2
0603
NOTE: Table 6, lists component sizes
shown in this layout example.
TABLE 6. FOOTPRINT TABLE
REVISION B 4/6/15
843002-01 DATA SHEET
11 FemtoClock
®
Crystal-to-3.3V LVPECL
Frequency Synthesizer
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 843002-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 843002-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 10% = 3.63V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.63V * 135mA = 490mW
• Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power
_MAX
(3.63V, with all outputs switching) = 490mW + 60mW = 550mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125°C.
The equation for Tj is as follows: Tj = θ
JA
* Pd_total + T
A
Tj = Junction Temperature
θ
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
JA
must be used. Assuming
a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.550W * 66.6°C/W = 121.6°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow,
and the type of board (single layer or multi-layer).
θ
JA
by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 7. THERMAL RESISTANCE θ
JA
FOR 20-PIN TSSOP, FORCED CONVECTION
FemtoClock
®
Crystal-to-3.3V LVPECL
Frequency Synthesizer
843002-01 DATA SHEET
12 REVISION B 4/6/15
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V
CCO
- 2V.
• For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
– 0.9V
(V
CCO_MAX
- V
OH_MAX
)
= 0.9V
• For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
– 1.7V
(V
CCO_MAX
- V
OL_MAX
)
= 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))
/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))
/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 5. LVPECL DRIVER CIRCUIT AND T ERMINATION
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

843002AG-01LF

Mfr. #:
Buy 843002AG-01LF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner 2 LVPECL OUT SYNTHESIZER
Lifecycle:
New from this manufacturer.
Delivery:
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