FemtoClock
®
Crystal-to-3.3V LVPECL
Frequency Synthesizer
843002-01 DATA SHEET
8 REVISION B 4/6/15
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply
pins are vulnerable to random noise. The 843002-01 pro-
vides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
, and
V
CCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each V
CCA
.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10Ω
V
CCA
10μF
.01μF
3.3V
.01μF
V
CC
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
FIGURE 2B. LVPECL OUTPUT T ERMINATIONFIGURE 2A. LVPECL OUTPUT T ERMINATION
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 2A and 2B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
