3
ICS95VLP857
0956B—08/03/04
Pin Descriptions
EMANNIPEPYTNOITPIRCSED
DDVRWPV5.2,ylppusrewoP
DNGRWPdnuorG
DDVARWPV5.2,ylppusrewopgolanA
DNGARWPdnuorggolanA
)0:9(TKLCTUOstuptuoriaplaitnereffidfokcolC"eurT"
)0:9(CKLCTUOstuptuoriaplaitnereffidfoskcolc"yratnemelpmoC"
CNI_KLCNItupnikcolcecnerefer"yratnemelpmoC"
TNI_KLCNItupnikcolcecnerefer"eurT"
CTUO_BFTUO
tI.kcabdeeflanretxerofdetacided,tuptuokcabdeeF"yratnemelpmoC"
deriwebtsumtuptuosihT.KLCehtsaycneuqerfemasehttasehctiws
CNI_BFot
TTUO_BFTUO
sehctiwstI.kcabdeeflanretxerofdetacided,tuptuokcabdeeF""eurT"
otderiwebtsumtuptuosihT.KLCehtsaycneuqerfemasehtta
TNI_BF
TNI_BFNI
rofLLPlanretniehtotlangiskcabdeefsedivorp,tupnikcabdeeF"eurT"
rorreesahpetanimileotTNI_KLChtiwnoitazinorhcnys
CNI_BFNI
LLPlanretniehtotlangissedivorp,tupnikcabdeeF"yratnemelpmoC"
rorreesahpetanimileotCNI_KLChtiwnoitazinorhcnysrof
#DPNItupniSOMCVL.nwoDrewoP
This PLL Clock Buffer is designed for a V
DD
of 2.5V, an AV
DD
of 2.5V and differential data input and output levels.
The ICS95VLP857 is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to ten
differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT,
FB_OUTC). The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT,
FB_INC), the 2.5-V LVCMOS input (PD#) and the Analog Power input (AV
DD
). When input (PD#) is low while power is
applied, the receivers are disabled, the PLL is turned off and the differential clock outputs are tri-stated. When AV
DD
is grounded, the PLL is turned off and bypassed for test purposes.
When the input frequency is less than the operating frequency of the PLL, appproximately 20MHz, the device will enter
a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers,
will detect the low frequency condition and perform the same low power features as when the (PD#) input is low. When
the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and
outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input
clock pair (CLK_INC, CLK_INT).
The PLL to the ICS95VLP857 clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks
(FB_INT, FB_INC) provide high-performance, low-skew, low-jitter, output differential clocks (CLKT[0:9], CLKC[0:9]).
The ICS95VLP857 is also able to track Spread Spectrum Clock (SSC) for reduced EMI.
The ICS95VLP857 is characterized for operation from 0°C to 85°C, and will meet JEDEC Standard 82-1 and 82-1A Class
A+ for registered DDR clock drivers.
