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95VLP857AHLFT

P1-P3P4-P6P7-P9P10-P12P13-P13
4
ICS95VLP857
0956B—08/03/04
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD). . . . . . . . . . . -0.5V to 4.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V
DD
+ 0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 85°C; Supply Voltage A
VDD
, V
DD
= 2.5V ± 0.2V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Current I
IH
V
I
= V
DD
or GND 5 µA
Input Low Current I
IL
V
I
= V
DD
or GND 5 µA
I
DD2.5
C
L
= 0pf @ 200MHz 125 150 mA
I
DDPD
C
L
= 0pf 100 µA
Output High Current I
OH
V
DD
= 2.3V, V
OUT
= 1V -18 -32 mA
Output Low Current I
OL
V
DD
= 2.3V, V
OUT
= 1.2V 26 35 mA
High Impedance
Out
p
ut Current
I
OZ
V
DD
=2.7V, Vout=V
DD
or GND ±10 mA
Input Clamp Voltage V
IK
V
DDQ
= 2.3V Iin = -18mA -1.2
V
V
DD
= min to max,
I
OH
= -1 mA
V
DDQ
- 0.1 V
V
DDQ
= 2.3V,
I
OH
= -12 mA
1.7 V
V
DD
= min to max
I
OL
=1 mA
0.1 V
V
DDQ
= 2.3V
I
OH
=12 mA
0.6 V
Input Capacitance
1
C
IN
V
I
= GND or V
DD
3pF
Output Capacitance
1
C
OUT
V
OUT
= GND or V
DD
3pF
1
Guaranteed by design at 220MHz, not 100% tested in production.
Operating Supply
Current
High-level output
voltage
V
OH
Low-level output voltage V
OL
5
ICS95VLP857
0956B—08/03/04
Recommended Operating Condition
(
see note1
)
T
A
= 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage V
DD
, A
VDD
2.3 2.5 2.7 V
CLKT, CLKC, FB_INC 0.4 V
DD
/2 - 0.18 V
PD# -0.3 0.7 V
CLKT, CLKC, FB_INC V
DD
/2 + 0.18 2.1 V
PD# 1.7 V
DD
+ 0.6 V
DC input signal voltage
(note 2)
V
IN
-0.3 V
DD
+ 0.3 V
DC - CLKT, FB_INT 0.36 V
DD
+ 0.6 V
AC - CLKT, FB_INT 0.7 V
DD
+ 0.6 V
Output differential cross
-
voltage (note 4)
V
OX
V
DD
/2 - 0.15 V
DD
/2 + 0.15 V
Input differential cross-
voltage (note 4)
V
IX
V
DD
/2 - 0.2 V
DD
/2 V
DD
/2 + 0.2 V
High level output
current
I
OH
-6.4 mA
Low level output current I
OL
5.5 mA
Operating free-air
temperature
T
A
085°C
Differential input signal
voltage (note 3)
V
ID
Low level input voltage V
IL
High level input voltage V
IH
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VT is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of V
DD
and is the
voltage at which the differential signal must be crossing.
6
ICS95VLP857
0956B—08/03/04
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=t
wH
/t
c
, where
the cycle (t
c
) decreases as the frequency goes up.
3. Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
Timing Requirements
T
A
= 0 - 85°C; Supply Voltage A
VDD
, V
DD
= 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN MAX UNITS
Max clock frequency freq
op
2.5V+0.2V @ 25
o
C
45 233 MHz
Application Frequency
Range
freq
App
2.5V+0.2V @ 25
o
C
95 220 MHz
Input clock duty cycle d
tin
40 60 %
CLK stabilization T
STAB
15 µs
Switching Characteristics (see note 3)
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS
Low-to high level
propagation delay time
t
PLH
1
CLK_IN to any output 3.5 ns
High-to low level propagation
delay time
t
PLL
1
CLK_IN to any output 3.5 ns
Output enable time t
EN
PD# to any output 3 ns
Output disable time tdis PD# to any output 3 ns
Period jitter T
j
it
(p
er
)
100MHz to 200MHz -30 30 ps
Half-period jitter t(jit_hper) 100MHz to 200MHz -75 75 ps
Input clock slew rate t
sl
(
i
)
14V/ns
Output clock slew rate t
sl
o
12V/ns
Cycle to Cycle Jitter
1
T
c
y
c
-T
c
y
c
100MHz to 200MHz -50 50 ps
Static Phase Offset
t
(
static
p
hase offset
)
4
-50 0 50 ps
Output to Output Skew T
skew
40 ps
P1-P3P4-P6P7-P9P10-P12P13-P13

95VLP857AHLFT

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IC CLK BUF DDR 233MHZ 1CIRC
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