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74HC21PW,118
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
74HC21
All information pr
ovided in this d
ocument is su
bject to legal dis
claimers.
© NXP Semiconduc
tors N.V
. 201
5. All rights rese
rved.
Product data sheet
Rev
. 7 — 30 November 2015
6 of 14
NXP Semiconductors
74HC21
Dual 4-input AND gate
1
1. W
aveforms
Measurement points are given in
T
able 8
.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 7.
Wave
forms showi
ng the inpu
t (nA, nB, nC, nD) to ou
tput (nY) prop
agation dela
ys and the o
utput
transition times
D
DE
Q$Q%
Q&
Q'LQS
XW
Q<
RXW
S
XW
9
0
9
;
9
,
W
3+/
W
7+/
W
7/+
W
3/+
9
2+
9
0
9
<
9
2/
*1'
T
able 8.
Measur
ement point
s
Ty
p
e
Input
Output
V
M
V
M
V
X
V
Y
74HC21
0.5V
CC
0.5V
CC
0.1V
CC
0.9V
CC
74HC21
All information pr
ovided in this d
ocument is su
bject to legal dis
claimers.
© NXP Semiconduc
tors N.V
. 201
5. All rights rese
rved.
Product data sheet
Rev
. 7 — 30 November 2015
7 of 14
NXP Semiconductors
74HC21
Dual 4-input AND gate
T
est data is given in
T
able 9
.
Definitions test circuit:
R
T
= termination resistance should be equal to output impedance Z
o
of the pulse generator
.
C
L
= load capacitance including jig and probe capacitance.
Fig 8.
T
est circuit for me
asuring switching
times
DD
K
W
:
W
:
W
U
W
U
W
I
9
0
9
,
QHJD
WLYH
SXO
VH
*1'
9
,
SRVLW
LYH
SXOVH
*1'
9
0
9
0
9
0
W
I
9
&&
'87
5
7
9
,
9
2
&
/
*
T
able 9.
T
est data
Ty
p
e
Input
Load
Te
s
t
V
I
t
r
, t
f
C
L
74HC21
V
CC
6.0 ns
15 pF
, 50
pF
t
PLH
, t
PHL
74HC21
All information pr
ovided in this d
ocument is su
bject to legal dis
claimers.
© NXP Semiconduc
tors N.V
. 201
5. All rights rese
rved.
Product data sheet
Rev
. 7 — 30 November 2015
8 of 14
NXP Semiconductors
74HC21
Dual 4-input AND gate
12. Package
outline
Fig 9.
Package outline SOT108-1 (SO1
4)
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627
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
74HC21PW,118
Mfr. #:
Buy 74HC21PW,118
Manufacturer:
Nexperia
Description:
Logic Gates AND 2CIRCUIT 6V
Lifecycle:
New from this manufacturer.
Delivery:
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